Memory device and divided clock correction method thereof

Patent metadata

Field	Value
Publication number	US-11056158-B2
Application number	US-201916571868-A
Country	US
Kind code	B2
Filing date	Sep 16, 2019
Priority date	Sep 26, 2016
Publication date	Jul 6, 2021
Grant date	Jul 6, 2021

Abstract

A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.

First claim

What is claimed is:

1. A memory device comprising:
an internal clock generator that is configured to generate a plurality of internal clock signals by dividing a received clock signal, where each of the internal clock signals has a respective phase that is different from the phases of the other internal clock signals;
a serializer that is configured to use the internal clock signals to serialize training data;
a data output buffer that is configured to output the serialized training data; and
a clock controller that is configured to correct a clock dividing start time point of the received clock signal based on a control signal provided by a host,
wherein a value of the control signal is based on a time that the serialized training data was received at the host.

2. The memory device of claim 1 , wherein a data output buffer that is configured to output the serialized training data through a dedicated EDC pad is distinguished from a data pad through which write data is output.

3. The memory device of claim 1 , wherein the control signal comprises a mode register set code.

4. The memory device of claim 1 , further comprising a register that stores the training data prior to serialization of the training data.

5. The memory device of claim 4 , wherein the training data is provided to the memory device from the host.

6. The memory device of claim 5 , wherein a data rate of the serialized training data is greater than a data rate of the training data from the register.

7. The memory device of claim 3 , wherein the control signal that is received from the host has a different value than a prior version of the control signal that is stored in the memory device when the serialized training data is received out of order at the host.

8. A method for correcting a clock dividing start time point of a memory device, the method comprising:
sampling serial test data that is received from a host using a plurality of internal clock signals to deserialize the serial test data, wherein the serial test data is sampled using one of a rising edge or a falling edge of each of the internal clock signals; and
configuring the memory device to sample data that is received from the host using an other one of the rising edge or the falling edge of each of the internal clock signals responsive to a determination that the deserialized serial test data was deserialized out of order.

9. The method of claim 8 , wherein the internal clock signals are generated by dividing a clock signal that is received from the host.

10. The method of claim 9 , further comprising aligning the deserialized serial test data to generate aligned test data.

11. The method of claim 10 , further comprising comparing the aligned test data to reference data to determine if the serial test data was deserialized out of order.

12. The method of claim 8 , wherein each of the internal clock signals has a respective phase that is different from the phases of the other internal clock signals.

13. A method for correcting a clock dividing start time point of a memory device, the method comprising:
serializing test data to provide a serialized data pattern using a plurality of internal clock signals that are generated by dividing a clock signal that is received from the host;
comparing reference data with the serialized data pattern; and
correcting the clock dividing start time point of the clock signal based on the comparison of the reference data with the serialized data pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Dong-Seok
• Bae Seungjun

Classifications

• G11C2207/107

  Serial-parallel conversion of data or prefetch · CPC title

• G11C29/56012

  Timing aspects, clock generation, synchronisation · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title