Embedded bridge with through-silicon Vias

Patent metadata

Field	Value
Publication number	US-11049798-B2
Application number	US-201916457336-A
Country	US
Kind code	B2
Filing date	Jun 28, 2019
Priority date	Jun 30, 2017
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

First claim

We claim:

1. An integrated circuit (IC) package, comprising:
a substrate, and a bridge die within the substrate, the bridge die comprising a plurality of vias extending from a first side to a second side of the bridge die, wherein the bridge die comprises a first plurality of pads on the first side and a second plurality of pads on the second side, wherein the plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads, and wherein the bridge die comprises an adhesive film over a layer of silicon oxide, the layer of silicon oxide in contact with the second side of the bridge die and in contact with the adhesive film.

2. The IC package of claim 1 , wherein at least a portion of the second plurality of pads on the second side of the bridge die is electrically coupled to a trace routing in the substrate.

3. The IC package of claim 1 , wherein at least a portion of the first plurality of pads on the first side of the bridge die is electrically coupled to pads on a surface of the substrate.

4. The IC package of claim 1 , wherein sidewalls of the ones of the second plurality of pads are adjacent to the layer of silicon oxide, and wherein tops of the ones of the second plurality of pads are planar with the layer of silicon oxide and are within openings in the adhesive film.

5. The IC package of claim 1 , wherein the adhesive film is over the ones of the second plurality of pads.

6. The IC package of claim 5 , wherein the adhesive film comprises conductive particles.

7. The IC package of claim 1 , wherein the adhesive film is a die backside film.

8. The IC package of claim 1 , wherein the adhesive film is an epoxy flux film.

9. The IC package of claim 1 , wherein the adhesive film is an epoxy flux paste.

10. The IC package of claim 1 , wherein the adhesive film is a wafer-level under film.

11. The IC package of claim 1 , wherein the adhesive film surrounds solder joints and between the ones of the second plurality of pads.

12. The IC package of claim 1 , wherein the bridge die is within a cavity in the substrate.

13. The IC package of claim 12 , wherein the adhesive film is adhesively bonded to a wall of the cavity.

14. The IC package of claim 1 , wherein the adhesive film is electrically conducive and wherein the adhesive film couples the second plurality of pads to a conductive layer within the substrate.

15. The IC package of claim 1 , wherein the first plurality of pads is electrically coupled to a conductive layer on a surface of the substrate.

16. The IC package of claim 1 , wherein the-bridge die comprises silicon.

17. A system comprising:
a first active die coupled to a substrate; and
a second active die coupled to the substrate, wherein: the substrate comprises a bridge die within a cavity, the bridge die comprising a plurality of vias extending from a first side to a second side of the bridge die, wherein the bridge die comprises a first plurality of pads on the first side and a second plurality of pads on the second side, wherein the plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads, and wherein the bridge die comprises an adhesive film over a layer of silicon oxide, the layer of silicon oxide in contact with the second side of the bridge die and in contact with the adhesive film, wherein ones of the first plurality of pads are coupled to a first signal routing on the first active die and to a second signal routing on the second active die.

18. The system of claim 17 , wherein the first signal routing is coupled to the second signal routing by traces on the first side of the bridge die extending between ones of the first plurality of pads.

19. The system of claim 17 , wherein the second plurality of pads is coupled to power routing traces in the substrate.

20. The system of claim 19 , wherein an adhesive conductive film couples the second plurality of pads to the power routing traces in the substrate.

Assignees

• Intel Corp

Inventors

• Vaidya Aditya S
• Mahajan Ravindranath V
• Raorane Digvijay A
• Start Paul R

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/073

  of die-attach connectors · CPC title