Programmable logic circuit for controlling an electrical facility, in particular a nuclear facility, associated control device and method

Patent metadata

Field	Value
Publication number	US-11043949-B2
Application number	US-201816492112-A
Country	US
Kind code	B2
Filing date	Mar 8, 2018
Priority date	Mar 8, 2017
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

A programmable logic circuit (10) for controlling an electrical facility, in particular a nuclear facility, includes an operating unit (14). The operating unit includes a plurality of types of functional blocks (FB1, FBi, FBN), two distinct types of functional blocks being suitable for executing at least one distinct function, at least one processing module suitable for receiving at least one sequence (46) of functional block(s) to be executed, and at least one internal memory (38) configured to store at least said sequence (46). The programmable logic circuit (10) includes a single functional block of each type, a given functional block being suitable for being called several times, and an execution module (22) configured to execute the called functional block(s) in series, according to said sequence (46).

First claim

What is claimed is:

1. A programmable logic circuit for controlling an electrical facility, the programmable logic circuit comprising an operating unit comprising:
a plurality of types of functional blocks, two distinct types of the functional blocks being configured for executing at least one distinct function;
at least one processing module configured for receiving at least one sequence of the functional block(s) to be executed; and
at least one internal memory configured to store at least the sequence, the programmable logic circuit including a single functional block of each type of the functional blocks, a given functional block being configured for being called several times, and an execution module configured to execute at least one called functional block in series, according to the sequence.

2. The programmable logic circuit according to claim 1 , wherein the programmable logic circuit is of a FPGA type.

3. The programmable logic circuit according to claim 1 , wherein the execution module is a finite-state machine.

4. The programmable logic circuit according to claim 1 , wherein the operating unit further comprises a plurality of parallelizable floating point units.

5. The programmable logic circuit according to claim 1 , wherein the at least one processing module is configured for receiving an application program corresponding to a group of computer configuration files comprising the sequence and at least one other computer file belonging to the group comprising:
a configuration file of the memory corresponding to a table associating, with at least one input/output signal of the programmable logic circuit, an address in its memory,
a file with value(s) of parameter(s) of functional block(s) configured for executing at least one function using a parameter,
a file listing, for each functional block, the address or addresses of the memory allocated to one or more input(s) of this functional block,
a file listing, for each functional block, the address or addresses of the memory allocated to one or more output(s) of this functional block.

6. The programmable logic circuit according to claim 5 , wherein the parameter values are sequenced within their file as a function of the sequence of functional block(s) to be executed.

7. The programmable logic circuit according to claim 1 , wherein the memory comprises at least two data storage areas respectively dedicated to binary data and analog data.

8. The programmable logic circuit according to claim 7 , wherein each storage area comprises at least three dedicated subareas:
at least one subarea dedicated to the input data of the programmable logic circuit,
at least one subarea dedicated to the output data of the programmable logic circuit, and
at least one subarea dedicated to temporary data obtained during execution of the sequence.

9. The programmable logic circuit according to claim 8 , wherein the subareas dedicated to the input data or the subareas dedicated to the output data are synchronous flip-flop registers.

10. A control device for controlling an electrical facility, wherein the control device comprises at least one programmable logic circuit according to claim 1 .

11. The control device according to claim 10 , wherein the control device comprises a plurality of the programmable logic circuits.

12. The control device according to claim 11 , comprising a fiber-optic communication network configured to link the plurality of programmable logic circuits.

13. The control device according to claim 12 , wherein a master programmable logic circuit, among the plurality of programmable logic circuits, is configured for being connected to a clock and is configured to synchronize the other programmable logic circuits of the plurality of programmable logic circuits by means of the fiber-optic communication network.

14. The control device according to claim 13 , wherein the master programmable logic circuit is also configured to synchronize the auxiliary modules by the communication bus.

15. The control device according to claim 11 , wherein the plurality of programmable logic circuits is housed in a same rack.

16. The control device according to claim 11 , wherein the programmable logic circuits of the plurality of programmable logic circuits are separated in at least two distinct racks.

17. The control device according to claim 10 , further comprising:
at least one power module;
auxiliary modules among one or several modules dedicated to acquiring distinct input data, one or several modules dedicated to publishing distinct output data, and one or several service maintenance diagnosis modules; and
a communication bus configured to link the at least one programmable logic circuit to the auxiliary modules.

18. The control device according to claim 17 , wherein the communication bus comprises four multipoint-low voltage differential signaling links respectively dedicated to the input data and the output data of each programmable logic circuit in each transmission direction.

Assignees

• Framatome Sa

Inventors

• Allory Mathieu
• Dupuy Nicolas

Classifications

• H03K19/17764 Primary

  for reliability · CPC title

• G21D3/008

  Man-machine interface, e.g. control room layout · CPC title

• G21D3/00

  Control of nuclear power plant (control of nuclear reaction in general G21C7/00) · CPC title

• G21D3/001

  Computer implemented control · CPC title

• H03K19/17728 Primary

  Reconfigurable logic blocks, e.g. lookup tables · CPC title