Integrated circuit device

Patent metadata

Field	Value
Publication number	US-11043553-B2
Application number	US-201916520912-A
Country	US
Kind code	B2
Filing date	Jul 24, 2019
Priority date	Sep 19, 2018
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a lower electrode;
an upper electrode; and
a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure comprising a first surface facing the lower electrode and a second surface facing the upper electrode, the dielectric layer structure including
a first dielectric layer comprising a first dielectric material and a plurality of grains extending from the first surface to the second surface; and
a second dielectric layer comprising a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer at a level lower than the second surface, the second dielectric material comprising a material having bandgap energy which is higher than bandgap energy of the first dielectric material,

wherein a portion of the sidewall of each of the plurality of grains of the first dielectric layer at a level adjacent to the second surface is not surrounded by the second dielectric layer.

2. The integrated circuit device of claim 1 , wherein the second dielectric material comprises a material having a melting point lower than a melting point of the first dielectric material.

3. The integrated circuit device of claim 1 , wherein
one of the plurality of grains comprises:
a first sidewall at a first vertical level; and
a second sidewall at a second vertical level closer to the second surface of the first dielectric layer than the first vertical level,
the first sidewall contacts the second dielectric layer, and
the second sidewall contacts at least one other grain of the plurality of grains.

4. The integrated circuit device of claim 1 , wherein
the first dielectric layer has a first thickness in a first direction vertical to the first surface of the dielectric layer structure, and
the second dielectric layer has a second thickness less than the first thickness of the first dielectric layer in the first direction.

5. The integrated circuit device of claim 1 , wherein
the second dielectric layer is not exposed at the second surface of the dielectric layer structure, and
the second dielectric layer is not exposed at the first surface of the dielectric layer structure.

6. The integrated circuit device of claim 1 , wherein
the second dielectric layer comprises a first portion and a second portion closer to the second surface than the first portion,
the first portion has a first width in a second direction parallel to the first surface, and
the second portion has a second width smaller than the first width of the first portion in the second direction.

7. The integrated circuit device of claim 1 , wherein the second dielectric layer is exposed at the first surface of the dielectric layer structure.

8. The integrated circuit device of claim 1 , wherein the dielectric layer structure further comprises a third dielectric layer between the first dielectric layer and the upper electrode.

9. The integrated circuit device of claim 1 , wherein the second dielectric layer comprises:
a lower second dielectric layer surrounding a lower portion of the sidewall of each of the plurality of grains of the first dielectric layer; and
an upper second dielectric layer spaced apart from the lower second dielectric layer and surrounding an upper portion of the sidewall of each of the plurality of grains of the first dielectric layer.

10. The integrated circuit device of claim 1 , wherein the second dielectric material comprises at least one of boron oxide (B 2 O 3 ), gallium oxide (Ga 2 O 3 ), and indium oxide (In 2 O 3 ).

11. The integrated circuit device of claim 1 , wherein the first dielectric material comprises at least one of zirconium oxide, hafnium oxide, titanium oxide, niobium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium strontium titanium oxide, scandium oxide, and lanthanons oxide.

12. An integrated circuit device comprising:
a lower electrode;
an upper electrode; and
a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure comprising a first surface facing the lower electrode and a second surface facing the upper electrode, the dielectric layer structure including
a first dielectric layer comprising a first dielectric material and a plurality of grains extending from the first surface to the second surface; and
a second dielectric layer comprising a second dielectric material differing from the first dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer at a level lower than the second surface,

wherein the first dielectric layer has a first thickness in a first direction vertical to the first surface, and the second dielectric layer has a second thickness less than the first thickness in the first direction,
wherein a portion of the sidewall of each of the plurality of grains of the first dielectric layer at a level adjacent to the second surface is not surrounded by the second dielectric layer.

13. The integrated circuit device of claim 12 , wherein
the second dielectric layer comprises a first portion closer to the first surface and a second portion closer to the second surface,
the first portion has a first width in a second direction parallel to the first surface, and
the second portion has a second width smaller than the first width in the second direction.

14. The integrated circuit device of claim 12 , wherein
one of the plurality of grains comprises:
a first sidewall at a first vertical level; and
a second sidewall at a second vertical level closer to the second surface of the first dielectric layer than the first vertical level,
the first sidewall contacts the second dielectric layer, and
the second sidewall contacts at least one other grain of the plurality of grains.

15. The integrated circuit device of claim 12 , wherein
the second dielectric layer is not exposed at the second surface of the dielectric layer structure, and
the second dielectric layer is not exposed at the first surface of the dielectric layer structure.

16. The integrated circuit device of claim 12 , wherein the second dielectric layer is exposed at the first surface of the dielectric layer structure.

17. The integrated circuit device of claim 12 , wherein the second dielectric layer comprises:
a lower second dielectric layer surrounding a lower portion of the sidewall of each of the plurality of grains of the first dielectric layer; and
an upper second dielectric layer spaced apart from the lower second dielectric layer and surrounding an upper portion of the sidewall of each of the plurality of grains of the first dielectric layer.

18. An integrated circuit device comprising:
a lower electrode;
an upper electrode; and
a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure comprising a first surface facing the lower electrode and a second surface facing the upper electrode, the dielectric layer structure including
a first dielectric layer comprising a first dielectric material and a plurality of grains extending from the first surface to the second surface; and
a second dielectric layer comprising a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer at a level lower than the second surface, the second dielectric material comprising a material having a melting point lower than a melti

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Youn-Soo
• Ryu Seung-Min
• Woo Chang-Su
• Jung Hyung-Suk
• Cho Kyu-Ho
• Cho Youn-Joung

Classifications

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/68 Primary

  Capacitors having no potential barriers · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title

• H01L28/40 Primary

  Electricity · mapped topic

• H01L27/10814

  Electricity · mapped topic