Memory module with programmable command buffer

Patent metadata

Field	Value
Publication number	US-11042492-B2
Application number	US-201816631163-A
Country	US
Kind code	B2
Filing date	Oct 17, 2018
Priority date	Oct 24, 2017
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.

First claim

What is claimed is:

1. A memory module comprising:
a plurality of memory integrated circuit (IC) packages to store data; and
a command buffer IC to buffer a plurality of memory commands destined for the memory IC packages, the command buffer IC comprising:
a memory to store a set of pre-programmed reference command patterns each comprising a sequence of commands, each of the set of pre-programmed reference command patterns associated in the memory with one of a set of pre-programmed command sequences;
a first interface circuit to receive the plurality of memory commands; and
a pattern matching circuit to identify from the memory, a matching pre-programmed reference command pattern corresponding to the plurality of memory commands;
a sequence selector circuit to select a corresponding pre-programmed command sequence from the memory that is associated with the matching pre-programmed reference command pattern; and
one or more second interface circuits to output the corresponding pre-programmed command sequence to one or more devices separate from the command buffer IC.

2. The memory module of claim 1 , wherein the command buffer IC comprises:
a programming circuit to program the memory with the set of pre-programmed reference command patterns and the set of pre-programmed command sequences in response to information received by the command buffer IC.

3. The memory module of claim 1 , wherein the pre-programmed command sequence output by the one or more second interface circuits comprises at least one command for the plurality of memory IC packages.

4. The memory module of claim 1 , wherein the pre-programmed command sequence output by the one or more second interface circuits comprises at least one command for a non-volatile memory (NVM) controller circuit.

5. The memory module of claim 4 , wherein the at least one command for the NVM controller comprises an interrupt command.

6. The memory module of claim 1 , further comprising:
a plurality of data buffer ICs to buffer data transfers with the memory IC packages;
wherein the pre-programmed command sequence output by the one or more second interface circuits comprises at least one command for the data buffer ICs.

7. The memory module of claim 1 , wherein the first interface circuit is for coupling to a primary command channel, the first interface circuit to receive the plurality of memory commands from a memory controller via the primary command.

8. The memory module of claim 1 , wherein the first interface circuit is for coupling to a backup command channel, the first interface circuit to receive the plurality of memory commands from a non-volatile memory (NVM) controller via the backup command channel.

9. The memory module of claim 1 , wherein the pre-programmed command sequence causes data to be copied from the memory IC packages to non-volatile memory.

10. The memory module of claim 1 , wherein the command buffer IC comprises an internal functional circuit having a function that is controlled by one or more internal commands triggered responsive to the plurality of memory commands matching the pre-programmed reference command pattern.

11. A method of operation in system that comprises a memory module, the memory module comprising a command buffer integrated circuit (“IC”) and a plurality of memory IC packages to store data, the method comprising:
storing, by a memory, a set of pre-programmed reference command patterns each comprising a sequence of commands, each of the set of pre-programmed reference command patterns associated in the memory with one of a set of pre-programmed command sequences;
buffering, by the command buffer IC, a plurality of memory commands destined for the memory IC packages;
determining, by the command buffer IC, a matching pre-programmed reference command pattern from the memory corresponding to the plurality of memory commands;
selecting a corresponding pre-programmed command sequence from the memory that is associated with the matching pre-programmed reference command pattern; and
outputting the matching pre-programmed command sequence from the command buffer IC to one or more devices separate from the command buffer IC.

12. The method of claim 11 , further comprising:
programming the command buffer IC to include the set of pre-programmed reference command patterns and the set of pre-programmed command sequences in response to information received by the command buffer IC.

13. The method of claim 11 , wherein the pre-programmed command sequence comprises at least one command for the plurality of memory IC packages.

14. The method of claim 11 , wherein the pre-programmed command sequence comprises at least one command for a non-volatile memory (NVM) controller.

15. The method of claim 11 , wherein the memory module comprises a plurality of data buffer ICs to buffer data transfers with the memory IC packages;
wherein the pre-programmed command sequence comprises at least one command for the data buffer ICs.

16. The method of claim 11 further comprising:
receiving, at the command buffer IC, the plurality of memory commands from a memory controller via a primary command channel.

17. The method of claim 11 further comprising:
receiving, at the command buffer IC, the plurality of memory commands from a non-volatile memory (NVM) controller via a backup command channel.

18. A memory module comprising:
a plurality of data storage means for storing data; and
a buffer means for buffering a plurality of memory commands destined for the plurality of data storage means, storing a set of pre-programmed reference command patterns each comprising a sequence of commands, each of the set of pre-programmed reference command patterns associated in the memory with one of a set of pre-programmed command sequences, determining a matching pre-programmed reference command pattern from the memory corresponding to the plurality of memory commands selecting a corresponding pre-programmed command sequence from the memory that is associated with the matching pre-programmed reference command pattern, and outputting the matching pre-programmed command sequence to one or more devices separate from the buffer means.

Assignees

• Rambus Inc

Inventors

• Shallal Aws
• Giddens Larry Grant

Classifications

• G11C2207/104

  Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title