Data storage device with dynamic stripe length manager

Patent metadata

Field	Value
Publication number	US-11042432-B1
Application number	US-201916723513-A
Country	US
Kind code	B1
Filing date	Dec 20, 2019
Priority date	Dec 20, 2019
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

A memory controller includes, in one embodiment, a memory interface and a dynamic stripe length manager circuit configured to receive a first weighted health factor associated with a first memory block of the memory, determine a first collective stripe length of the first memory block based on the first weighted health factor, set a first number of zones in the first memory block based on the first collective stripe length, monitor the memory to detect a trigger event that triggers a calculation of a second collective stripe length of the first memory block, the second collective stripe length being larger than the first collective stripe length, receive a second weighted health factor associated with the first memory block, determine the second collective stripe length based on the second weighted health factor, and set a second number of zones in the first memory block based on the second collective stripe length.

First claim

What is claimed is:

1. A memory controller, comprising:
a memory interface configured to interface with a memory; and
a dynamic stripe length manager circuit configured to:
receive a first weighted health factor associated with a first memory block of the memory,
determine a first collective stripe length of the first memory block based on the first weighted health factor,
set a first number of zones in the first memory block based on the first collective stripe length,
monitor the memory to detect a trigger event that triggers a calculation of a second collective stripe length of the first memory block, the second collective stripe length being larger than the first collective stripe length,
receive a second weighted health factor associated with the first memory block,
determine the second collective stripe length based on the second weighted health factor, and
set a second number of zones in the first memory block based on the second collective stripe length.

2. The memory controller of claim 1 , wherein the first collective stripe length is determined based on the first weighted health factor and a first host protection level requirement, and wherein the second collective stripe length is determined based on the second weighted health factor and a second host protection level requirement.

3. The memory controller of claim 1 , wherein the dynamic stripe length manager circuit is further configured to
set a first size of respective stripe lengths in the first memory block based on the first collective stripe length, and
set a second size of second respective stripe lengths in the first memory block based on the second collective stripe length.

4. The memory controller of claim 3 , wherein the first size is larger than the second size.

5. The memory controller of claim 1 , wherein, to monitor the memory to detect the trigger event, the dynamic stripe length manager circuit is further configured to:
determine an idle window before a host write to the first memory block, and
calculate the second collective stripe length of the first memory block during the idle window.

6. The memory controller of claim 1 , wherein, to monitor the memory to detect the trigger event, the dynamic stripe length manager circuit is further configured to, after a successful read operation of the first memory block:
determine whether a number of read operations since the determination of the first collective stripe length exceeds a rebalancing threshold, and
calculate the second collective stripe length of the first memory block in response to the determining that the number of read operations since the determination of the first collective stripe length exceeds the rebalancing threshold.

7. The memory controller of claim 1 , wherein, to monitor the memory to detect the trigger event, the dynamic stripe length manager circuit is further configured to:
receive an indication of an observed read/program failure at the first memory block,
determine an overall wordline/page failure of the first memory block in response to receiving the indication,
determine whether the overall wordline/page is prone to more errors by comparing the overall wordline/page failure to a threshold, and
set a flag to allocate an increase in XOR/ECC to the wordlines/pages that are prone to more errors.

8. The memory controller of claim 7 , wherein the dynamic stripe length manager circuit is further configured to:
determine a die wordline/page failure in response to determining the overall wordline/page failure,
determine, with respect to the die, whether the overall wordline/page is prone to more errors by comparing the overall wordline/page failure to a second threshold, and
sets a flag to allocate an increase in XOR/ECC to other wordlines/pages on the die.

9. A method, comprising:
receiving, with a dynamic stripe length manager circuit, a first weighted health factor associated with a first memory block of a memory;
determining, with the dynamic stripe length manager circuit, a first collective stripe length of the first memory block based on the first weighted health factor;
setting, with the dynamic stripe length manager circuit, a first number of zones in the first memory block based on the first collective stripe length;
monitoring, with the dynamic stripe length manager circuit, the memory to detect a trigger event that triggers a calculation of a second collective stripe length of the first memory block, the second collective stripe length being larger than the first collective stripe length;
receiving, with the dynamic stripe length manager circuit, a second weighted health factor associated with the first memory block;
determining, with the dynamic stripe length manager circuit, the second collective stripe length based on the second weighted health factor; and
setting, with the dynamic stripe length manager circuit, a second number of zones in the first memory block based on the second collective stripe length.

10. The method of claim 9 , further comprising:
receiving a first host protection level requirement; and
receiving a second host protection level requirement,
wherein the first collective stripe length is determined based on the first weighted health factor and the first host protection level requirement, and the second collective stripe length is determined based on the second weighted health factor and the second host protection level requirement.

11. The method of claim 9 , further comprising:
setting a first size of respective stripe lengths in the first memory block based on the first collective stripe length; and
setting a second size of second respective stripe lengths in the first memory block based on the second collective stripe length.

12. The method of claim 11 , wherein the first size is larger than the second size.

13. The method of claim 9 , wherein monitoring the memory to detect the trigger event further includes:
determining an idle window before a host write to the first memory block, and
calculating the second collective stripe length of the first memory block during the idle window.

14. The method of claim 9 , wherein monitoring the memory to detect the trigger event further includes:
determining a successful a read operation of the first memory block,
determining whether a number of read operations since the determination of the first collective stripe length exceeds a rebalancing threshold, and
calculating the second collective stripe length of the first memory block in response to the determining that the number of read operations since the determination of the first collective stripe length exceeds the rebalancing threshold.

15. The method of claim 9 , wherein monitoring the memory to detect the trigger event further includes:
receiving an indication of an observed read/program failure at the first memory block,
determining an overall wordline/page failure of the first memory block in response to receiving the indication,
determining whether the overall wordline/page is prone to more errors by comparing the overall wordline/page failure to a threshold, and
setting a flag to allocate an increase in XOR/ECC to the wordlines/pages that are prone to more errors.

16. The method of claim 15 , further comprising:
determining a die wordline/page failure in response to determining the overall wordline/page failure,
determining, with respect to the die, whether the overall wordline/page is prone to more errors by comparing the overall wordline/page failure to a second threshold, and
setting a flag to allocate an increase in XOR/ECC to other wordl

Assignees

• Western Digital Tech Inc

Inventors

• Rao Abhijit
• Muthiah Ramanathan
• Hahn Judah Gamliel
• Dusija Gautam Ashok
• Linnen Daniel

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C2029/0409

  Online test · CPC title

• G06F11/108

  Parity data distribution in semiconductor storages, e.g. in SSD · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title