Method and apparatus for configuring write performance for electrically writable memory devices

Patent metadata

Field	Value
Publication number	US-11042313-B2
Application number	US-201816122510-A
Country	US
Kind code	B2
Filing date	Sep 5, 2018
Priority date	Dec 17, 2008
Publication date	Jun 22, 2021
Grant date	Jun 22, 2021

Abstract

Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory is associated with a configuration register to indicate a write speed setting for at least one write operation to the nonvolatile memory. A circuit may supply current to achieve an indicated write speed setting for the at least one write operation to the nonvolatile memory.

First claim

What is claimed is:

1. A method, comprising:
selecting, for a memory device having a plurality of memory cells, a write bandwidth for the memory device from a plurality of write bandwidths, wherein each write bandwidth of the plurality corresponds to a respective quantity of memory cells that are written concurrently;
determining, after selecting the write bandwidth for the memory device, a current setting for performing write operations of the memory device in accordance with the selected write bandwidth; and
performing a write operation on the plurality of memory cells using the determined current setting.

2. The method of claim 1 , further comprising:
reading a write bandwidth setting from a memory register, wherein selecting the write bandwidth is based at least in part on the write bandwidth setting.

3. The method of claim 1 , wherein selecting the write bandwidth is performed before writing information associated with the write operation.

4. The method of claim 1 , wherein selecting the write bandwidth is based at least in part on an operating environment of the memory device.

5. The method of claim 1 , wherein selecting the write bandwidth is based at least in part on whether the memory device is being operated in an end product.

6. The method of claim 1 , wherein selecting the write bandwidth comprises:
identifying a setting of a programmable switch; and
selecting the write bandwidth based at least in part on the setting of the programmable switch.

7. The method of claim 1 , wherein selecting the write bandwidth is based at least in part on a determined power consumption of a system that includes the memory device.

8. The method of claim 1 , wherein selecting the write bandwidth is based at least in part on a determined amount of current that can be supplied to the memory device.

9. The method of claim 8 , further comprising:
determining a change in an amount of current available to the memory device, wherein selecting the write bandwidth comprises adjusting the write bandwidth based at least in part on the change in the amount of current available to the memory device.

10. The method of claim 1 , wherein selecting the write bandwidth is based at least in part on a number of electronic components that are idle at a particular time.

11. The method of claim 1 , wherein performing the write operation comprises:
adapting an operation of a state machine based at least in part on the current setting.

12. The method of claim 1 , wherein performing the write operation comprises:
adapting a number of memory cells being written concurrently based at least in part on the write bandwidth.

13. An apparatus, comprising:
a memory comprising a plurality of memory cells; and
a processor in communication with the memory and configured to:
select a write bandwidth for the memory from a plurality of write bandwidths for the memory, wherein each write bandwidth of the plurality corresponds to a respective quantity of memory cells that are written concurrently;
determine, after selecting the write bandwidth for the memory, a current setting for performing write operations of the memory in accordance with the selected write bandwidth; and
perform one or more write operations on the plurality of memory cells based at least in part on the current setting for performing write operations of the memory.

14. The apparatus of claim 13 , further comprising:
a configuration register configured to indicate one of a plurality of write speed settings, wherein the processor is configured to:
select the write bandwidth based at least in part on the one of the plurality of write speed settings indicated by the configuration register.

15. The apparatus of claim 13 , wherein the processor is configured to:
determine an amount of power provided by a battery of the apparatus; and
select the write bandwidth based at least in part on the amount of power.

16. The apparatus of claim 13 , wherein the processor is configured to:
select the write bandwidth based at least in part on a power consumption determined by a power management device of the apparatus.

17. The apparatus of claim 16 , wherein the processor is configured to control the power management device to provide a current for the one or more write operations based at least in part on the current setting for performing write operations of the memory.

18. The apparatus of claim 13 , wherein the processor is configured to select the write bandwidth based at least in part on a determined power consumption of one or more electrical components of the apparatus.

19. The apparatus of claim 13 , further comprising:
a switch configured to indicate a number of bits that may be written at a time, wherein the processor is configured to:
select the write bandwidth based at least in part on the indicated number of bits that may be written at a time.

20. An apparatus, comprising:
one or more electrical components;
a memory comprising a plurality of memory cells; and
a processor in communication with the one or more electrical components and the memory, the processor configured to:
determine a current setting from a plurality of current settings for performing write operations of the memory based at least in part on a determined power consumption of the one or more electrical components;
determine a quantity of memory cells to be written concurrently based at least in part on the determined current setting; and
control a power management device to provide a current for one or more write operations on the plurality of memory cells based at least in part on the determined quantity of memory cells to be written concurrently.

Assignees

• Micron Technology Inc

Inventors

• Barkley Gerald
• Kale Poorna

Classifications

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C16/20

  Initialising; Data preset; Chip identification · CPC title

• G11C14/009

  and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C13/0038

  Power supply circuits · CPC title