Memory cell and an array of memory cells

Patent metadata

Field	Value
Publication number	US-11037942-B2
Application number	US-202016743088-A
Country	US
Kind code	B2
Filing date	Jan 15, 2020
Priority date	Jun 16, 2014
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.

First claim

The invention claimed is:

1. A memory cell, comprising:
a first upper electrode and a second lower electrode;
a select device and a programmable device in series with each other between the first and second electrodes, the select device being directly electrically coupled to the second lower electrode, the programmable device being directly electrically coupled to the first upper electrode; and
the programmable device comprising:
a radially inner electrode having radially outer sidewalls;
ferroelectric material radially outward of the radially outer sidewalls of the radially inner electrode;
a radially outer electrode radially outward of the ferroelectric material; and

the first upper electrode comprising a horizontally elongated line, the radially outer electrode directly electrically coupling with the horizontally elongated line, dielectric material elevationally between and directly against the radially inner electrode and an underside of the horizontally elongated line.

2. The memory cell of claim 1 wherein the dielectric material is also elevationally between the ferroelectric material and the underside of the horizontally elongated line.

3. The memory cell of claim 2 wherein the dielectric material is directly against an elevationally outermost surface of the ferroelectric material.

4. The memory cell of claim 1 wherein the ferroelectric material completely circumferentially surrounds the radially inner electrode in at least one horizontal cross section.

5. The memory cell of claim 1 wherein the radially outer electrode completely circumferentially surrounds the ferroelectric material in at least one horizontal cross section.

6. The memory cell of claim 1 wherein the radially outer electrode is of an upwardly open and downwardly open cylinder-like shape in a vertical cross section taken through an axial center of the radially outer electrode.

7. The memory cell of claim 1 wherein the ferroelectric material is of an upwardly open container-like shape in a vertical cross section taken through an axial center of the ferroelectric material.

8. The memory cell of claim 1 wherein the ferroelectric material is directly against one of the first upper electrode and the second lower electrode.

9. An array of the memory cells of claim 1 .

10. The memory cell of claim 1 wherein the radially inner electrode overall is wider at its top than at its bottom.

11. The memory cell of claim 1 wherein the radially outer electrode overall is wider at its top than at its bottom.

12. The memory cell of claim 1 wherein the ferroelectric material overall is wider at its top than at its bottom.

13. The memory cell of claim 1 wherein the ferroelectric material completely circumferentially surrounds the radially inner electrode in at least one horizontal cross section.

14. The memory cell of claim 1 wherein the radially outer electrode completely circumferentially surrounds the ferroelectric material in at least one horizontal cross section.

15. A memory cell, comprising:
a first upper electrode and a second lower electrode;
a select device and a programmable device in series with each other between the first and second electrodes, the select device being directly electrically coupled to the lower second electrode, the programmable device being directly electrically coupled to the upper first electrode; and
the programmable device comprising:
a radially inner electrode having radially outer sidewalls and having an upwardly open cylinder-like shape in a vertical cross section taken through an axial center of the radially inner electrode;
ferroelectric material radially outward of the radially outer sidewalls of the radially inner electrode;
a radially outer electrode radially outward of the ferroelectric material and directly electrically coupled to the first upper electrode; and

dielectric material radially within the upwardly open cylinder-like shape of the radially inner electrode, the dielectric material extending elevationally upward of the radially inner electrode and elevationally over tops of the radially inner electrode in the vertical cross section.

16. The memory cell of claim 15 wherein the dielectric material is directly against said tops.

17. The memory cell of claim 15 wherein the dielectric material is also elevationally over tops of the ferroelectric material in the vertical cross section.

18. The memory cell of claim 17 wherein the dielectric material is directly against said tops of the radially inner electrode and directly against said tops of the ferroelectric material.

19. The memory cell of claim 15 wherein the radially outer electrode is of an upwardly open and downwardly open cylinder-like shape in the vertical cross section.

20. The memory cell of claim 15 wherein the ferroelectric material is of an upwardly open container-like shape in the vertical cross section.

21. The memory cell of claim 15 wherein the radially inner electrode is of an upwardly open container-like shape in the vertical cross section.

22. The memory cell of claim 15 wherein the ferroelectric material is directly against one of the first upper electrode and the second lower electrode.

23. An array of the memory cells of claim 15 .

24. The memory cell of claim 15 wherein the radially inner electrode overall is wider at its top than at its bottom.

25. The memory cell of claim 15 wherein the radially outer electrode overall is wider at its top than at its bottom.

26. The memory cell of claim 15 wherein the ferroelectric material overall is wider at its top than at its bottom.

Assignees

• Micron Technology Inc

Inventors

• Ramaswamy Durai Vishak Nirmal
• Kinney Wayne
• Tiburzi Marco Domenico

Classifications

• H10D1/716

  having vertical extensions · CPC title

• H10D1/682 Primary

  having dielectrics comprising perovskite structures · CPC title

• G11C11/21

  using electric elements · CPC title

• G11C11/24

  using capacitors (G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40) · CPC title

• H01L28/55

  Electricity · mapped topic