Method and apparatus for forming backside die planar devices and saw filter

Patent metadata

Field	Value
Publication number	US-11037896-B2
Application number	US-201816216881-A
Country	US
Kind code	B2
Filing date	Dec 11, 2018
Priority date	Aug 7, 2014
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on the backside, the one or more passive planar devices formed in the RDL.

First claim

We claim:

1. An apparatus comprising:
a die having a back-side and a front-side, wherein the back-side of the die includes one or more passive devices in or on a redistribution layer (RDL), wherein the front-side of the die includes one or more active devices, and wherein the one or more passive devices are positioned in one or more regions in or on the RDL;
bumps directly coupled to the one or more passive devices;
a first layer including piezoelectric material, wherein the layer is adjacent to the one or more passive devices; and
a second layer including passivation material, wherein the second layer is adjacent to the first layer.

2. The apparatus of claim 1 , wherein the die is a first die, and wherein the apparatus comprises a second die coupled to the first die.

3. The apparatus of claim 2 , wherein the second die is coupled to the first die via the back-side of the first die.

4. The apparatus of claim 1 , wherein the one or more passive planar devices is one or more of: a SAW filter; a capacitive gap stripline band-pass filter; a stripline inter-digital filter; a stripline hairpin filter; a stripline stub filter fractal-shape microstrip filter; a stepped-impedance filter; a stepped-impedance filter with a shunt resonator; a butterfly stub; double stubs, a radial stub, paralleled radial stubs, a clover-leaf stub; a short-circuit stud; an open-circuit stub; a coplanar waveguide; a microstrip antenna; or stripline slot antenna.

5. The apparatus of claim 1 , wherein the one or more active devices include a low noise amplifier.

6. The apparatus of claim 1 , further comprising one or more vias to couple the one or more active devices with the one or more passive devices.

7. An apparatus comprising:
a die having a back-side and a front-side, wherein the back-side of the die includes:
a receiver SAW filter in or on a redistribution layer (RDL);
a transmitter SAW filter in or on the RDL; and
an antenna in or on the RDL,

and wherein the front-side of the die includes:
a low noise amplifier (LNA) coupled to the receiver SAW filter; and
a power amplifier (PA) coupled to the transmitter SAW filter; and

one or more vias coupled to the back-side and the front-side of the die.

8. The apparatus of claim 7 , wherein the back-side of the die includes a Bragg Reflector.

9. The apparatus of claim 8 , further comprising a layer including piezoelectric material, wherein the layer is adjacent to the SAW filter.

10. The apparatus of claim 9 , wherein the layer is a first layer, wherein the apparatus further comprises a second layer including passivation material, and wherein the second layer is adjacent to the first layer.

11. The apparatus of claim 7 , wherein the back-side of the die includes:
a receiver interstage SAW filter coupled to an output of the LNA; and
a transmitter interstage SAW filter coupled in an input of the PA.

12. The apparatus of claim 11 , wherein the front-side of the die includes:
a first mixer coupled to the receiver interstage SAW filter;
a second mixer coupled to the transmitter interstage SAW filter; and
a voltage controlled oscillator (VCO) coupled to the first mixer and the second mixer.

13. The apparatus of claim 7 , wherein the die is a first die, and wherein the apparatus comprises a second die coupled to the first die.

14. The apparatus of claim 13 , wherein the second die is coupled to the first die via the back-side of the first die.

15. The apparatus of claim 13 , wherein the second die comprises a baseband digital signal processor.

16. A system comprising:
a memory;
a processor coupled to the memory, wherein the processor includes:
a die having a back-side and a front-side, wherein the back-side of the die includes one or more passive devices in or on a redistribution layer (RDL), wherein the front-side of the die includes one or more active devices, and wherein the one or more passive devices are positioned in one or more regions in or on the RDL; and
bumps coupled to the one of more passive devices; and a display communicatively coupled to the processor;
a first layer including piezoelectric material, wherein the layer is adjacent to the one or more passive devices; and
a second layer including passivation material, wherein the second layer is adjacent to the first layer.

17. The system of claim 16 , wherein the die is a first die, and wherein the apparatus comprises a second die coupled to the first die.

18. The system of claim 17 , wherein the second die is coupled to the first die via the back-side of the first die.

Assignees

• Intel Corp

Inventors

• Lee Kevin J
• Saraswat Ruchir
• Zillmann Uwe
• Cowley Nicholas P
• Goldman Richard J

Classifications

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/922

  Bond pads being integral with underlying chip-level interconnections · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/654

  Top-view layouts · CPC title