Imprint-free write driver for ferroelectric memory

Patent metadata

Field	Value
Publication number	US-11037614-B2
Application number	US-201816615780-A
Country	US
Kind code	B2
Filing date	Jul 23, 2018
Priority date	Jul 28, 2017
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

Described is an apparatus to reduce or eliminate imprint charge, wherein the apparatus which comprises: a source line; a bit-line; a memory bit-cell coupled to the source line and the bit-line; a first multiplexer coupled to the bit-line; a second multiplexer coupled to the source-line; a first driver coupled to the first multiplexer; a second driver coupled to the second multiplexer; and a current source coupled to the first and second drivers.

First claim

We claim:

1. An apparatus comprising:
a source-line;
a bit-line;
a memory bit-cell coupled to the source-line and the bit-line;
a first multiplexer coupled to the bit-line;
a second multiplexer coupled to the source-line;
a first driver coupled to the first multiplexer;
a second driver coupled to the second multiplexer; and
a current source coupled to the first driver and the second drivers via a current mirror.

2. The apparatus of claim 1 , wherein the first driver comprises:
a first transistor, coupled to a resistor, wherein the first transistor is controllable by a signal to set a value in the memory bit-cell; and
a second transistor coupled in series with the first transistor, wherein the second transistor is to provide current.

3. The apparatus of claim 2 , wherein the resistor is a first resistor, wherein the second driver comprises:
a first transistor, coupled to a second resistor, wherein the first transistor of the second driver is controllable by a signal to reset the value in the memory bit-cell; and
a second transistor coupled in series with the first transistor, wherein the second transistor is to provide current.

4. The apparatus of claim 3 , wherein the second transistor of the first driver and the second transistor of the second driver are coupled to the current source.

5. The apparatus of claim 1 , wherein the memory bit-cell comprises a transistor coupled to a ferroelectric capacitor including ferroelectric material.

6. The apparatus of claim 5 , wherein the ferroelectric capacitor includes:
a first layer comprising metal;
a second layer comprising metal; and
two or more layers coupled between the first layer and the second layer, wherein the two or more layers include a first layer comprising a conductive oxide, a second layer comprising a conductive oxide, and a third layer comprising a perovskite, and wherein the third layer is adjacent to the first layer and the second layer.

7. The apparatus of claim 6 , wherein the two or more layers comprises a fourth layer adjacent to one of the first layer or the second layer, and wherein the fourth layer comprises a conductive seed layer.

8. The apparatus of claim 7 , wherein the fourth layer includes one of: Ti, Al, Nb, La, or Si.

9. The apparatus of claim 7 , wherein the first layer and the second layer of the two or more layers include one of: Sr, Ru, La, Sr, Mn, Nb, Cr, or O.

10. The apparatus of claim 7 , wherein the third layer includes one of: Sr, Ti, O, Bi, Fe, or Ba.

11. The apparatus of claim 7 , wherein the third layer includes a super lattice of PbTiO 3 (PTO) and SrTiO 3 (STO).

12. The apparatus of claim 11 , wherein the super lattice of PTO and STO are repeated in a range of 2 to 100 times.

13. The apparatus of claim 5 , wherein the transistor is coupled to a word-line.

14. An apparatus comprising:
a source-line;
a bit-line;
a memory bit-cell coupled to the source-line and the bit-line;
a first multiplexer coupled to the bit-line;
a second multiplexer coupled to the source-line;
a first driver coupled to the first multiplexer;
a second driver coupled to the second multiplexer;
a first current source coupled to the first driver via a first current mirror; and
a second current source coupled to the second driver via a second current mirror.

15. The apparatus of claim 14 , wherein the first driver comprises:
a first transistor, coupled to a resistor, wherein the first transistor is controllable by a signal to set a value in the memory bit-cell; and
a second transistor coupled in series with the first transistor, wherein the second transistor is to provide current.

16. The apparatus of claim 15 , wherein the resistor is a first resistor, wherein the second driver comprises:
a first transistor, coupled to a second resistor, wherein the first transistor of the second driver is controllable by a signal to reset the value in the memory bit-cell; and
a second transistor coupled in series with the first transistor, wherein the second transistor is to provide current.

17. The apparatus of claim 16 , wherein the second transistor of the first driver and the second transistor of the second driver are coupled to their respective current sources.

18. A system comprising:
a processor;
a memory coupled to the processor, the memory comprising:
a source-line;
a bit-line;
a memory bit-cell coupled to the source-line and the bit-line;
a first multiplexer coupled to the bit-line;
a second multiplexer coupled to the source-line;
a first driver coupled to the first multiplexer;
a second driver coupled to the second multiplexer; and
a current source coupled to the first driver and the second driver via a current mirror; and

a wireless interface to allow the processor to communicate with another device.

19. The system of claim 18 , wherein the first driver comprises:
a first transistor, coupled to a resistor, wherein the first transistor is controllable by a signal to set a value in the memory bit-cell; and
a second transistor coupled in series with the first transistor, wherein the second transistor is to provide current.

20. The system of claim 19 , wherein the resistor is a first resistor, wherein the second driver comprises:
a first transistor, coupled to a second resistor, wherein the first transistor of the second driver is controllable by a signal to reset the value in the memory bit-cell; and
a second transistor coupled in series with the first transistor, wherein the second transistor is to provide current.

Assignees

• Intel Corp

Inventors

• Liu Huichu
• Manipatruni Sasikanth
• Young Ian A
• Karnik Tanay
• Morris Daniel H
• Vaidyanathan Kaushik

Classifications

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• G11C11/221 Primary

  using ferroelectric capacitors · CPC title

• G11C11/2275 Primary

  Writing or programming circuits or methods · CPC title

• G11C11/2259

  Cell access · CPC title

• H01L27/11507

  Electricity · mapped topic