Element removal design in microwave filters

US11036910B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11036910-B2
Application numberUS-202016999528-A
CountryUS
Kind codeB2
Filing dateAug 21, 2020
Priority dateMar 15, 2013
Publication dateJun 15, 2021
Grant dateJun 15, 2021

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A method of designing a microwave filter using a computerized filter optimizer, comprises generating a filter circuit design in process (DIP) comprising a plurality of circuit elements having a plurality of resonant elements and one or more non-resonant elements, optimizing the DIP by inputting the DIP into the computerized filter optimizer, determining that one of the plurality of circuit elements in the DIP is insignificant, removing the one insignificant circuit element from the DIP, deriving a final filter circuit design from the DIP, and manufacturing the microwave filter based on the final filter circuit design.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: receiving, by a processor of a computing system, a first filter circuit model comprising a plurality of circuit elements, wherein the plurality of circuit elements comprises a plurality of resonant elements and one or more non-resonant elements; selectively removing one or more circuit elements of the plurality of circuit elements responsive to a comparison of a characteristic of each of the one or more circuit elements to a threshold value; and generating, by the processor, a second filter circuit model comprising a subset of the plurality of circuit elements that were not removed. 2. The method of claim 1 , wherein selectively removing one or more circuit elements further comprises iteratively removing one or more circuit elements responsive to the comparison and regenerating the first filter circuit model until no circuit element is removed. 3. The method of claim 2 , wherein, in a first iteration, a first circuit element is a nonresonant element. 4. The method of claim 3 , wherein regenerating the first circuit model in the first iteration further comprises one of: replacing the first circuit element with an equivalent capacitive element, responsive to the first circuit element comprising an inductive element; or replacing the first circuit element with an equivalent inductive element, responsive to the first circuit element comprising a capacitive element. 5. The method of claim 4 , further comprising, in a second iteration: determining that the first circuit element has previously been transformed between capacitive and inductive elements; and regenerating the first circuit model without the first circuit element, responsive to the determination that the first circuit element has previously been transformed between capacitive and inductive elements. 6. The method of claim 1 , wherein the characteristic of a first circuit element of the plurality of circuit elements is an impedance of the circuit element. 7. The method of claim 6 , wherein the first circuit element is a series inductor or shunt capacitor; and further comprising removing the first circuit element responsive to an absolute impedance of the first circuit element being less than the threshold value. 8. The method of claim 1 , wherein the characteristic of a first circuit element of the plurality of circuit elements is a resonant frequency, and the threshold comprises a frequency of a passband or stopband of a performance specification of the first filter circuit model. 9. The method of claim 1 , wherein a first circuit element is a resonant element, and wherein removing the first circuit element comprises replacing the first circuit element with a capacitor in the first filter circuit model. 10. A system, comprising: a processor executing an element removal design engine and a memory storing a first filter circuit model comprising a plurality of circuit elements, wherein the plurality of circuit elements comprises a plurality of resonant elements and one or more non-resonant elements; and wherein the element removal design engine is configured to: selectively remove one or more circuit elements of the plurality of circuit elements responsive to a comparison of a characteristic of each of the one or more circuit elements to a threshold value; and generate a second filter circuit model comprising a subset of the plurality of circuit elements that were not removed. 11. The system of claim 10 , wherein the element removal design engine is further configured to iteratively remove one or more circuit elements responsive to the comparison and regenerate the first filter circuit model until no circuit element is removed. 12. The system of claim 11 , wherein, in a first iteration, a first circuit element is a nonresonant element. 13. The system of claim 12 , wherein the element removal design engine is further configured to regenerate the first circuit model in the first iteration by either: replacing the first circuit element with an equivalent capacitive element, responsive to the first circuit element comprising an inductive element, or replacing the first circuit element with an equivalent inductive element, responsive to the first circuit element comprising a capacitive element. 14. The system of claim 13 , wherein the element removal design engine is further configured to, in a second iteration: determine that the first circuit element has previously been transformed between capacitive and inductive elements; and regenerate the first circuit model without the first circuit element, responsive to the determination that the first circuit element has previously been transformed between capacitive and inductive elements. 15. The system of claim 10 , wherein the characteristic of a first circuit element of the plurality of circuit elements is an impedance of the circuit element. 16. The system of claim 15 , wherein the first circuit element is a series inductor or shunt capacitor; and wherein the element removal design engine is further configured to remove the first circuit element responsive to an absolute impedance of the first circuit element being less than the threshold value. 17. The system of claim 10 , wherein the characteristic of a first circuit element of the plurality of circuit elements is a resonant frequency, and the threshold comprises a frequency of a passband or stopband of a performance specification of the first filter circuit model. 18. The system of claim 10 , wherein a first circuit element is a resonant element, and wherein the element removal design engine is further configured to replace the first circuit element with a capacitor in the first filter circuit model. 19. A non-transitory computer readable medium comprising instructions that, when executed by a processor of a computing device, cause the computing device to: receive a first filter circuit model comprising a plurality of circuit elements, wherein the plurality of circuit elements comprises a plurality of resonant elements and one or more nonresonant elements; selectively remove one or more circuit elements of the plurality of circuit elements responsive to a comparison of a characteristic of each of the one or more circuit elements to a threshold value; and generate a second filter circuit model comprising a subset of the plurality of circuit elements that were not removed. 20. The computer readable medium of claim 19 , further comprising instructions to cause the computing device to iteratively remove one or more circuit elements responsive to the comparison and regenerate the first filter circuit model until no circuit element is removed.

Assignees

Inventors

Classifications

  • H03H9/46Primary

    Filters (multiple-port electromechanical filters H03H9/70) · CPC title

  • H03H9/542Primary

    including passive elements (H03H9/545 takes precedence) · CPC title

  • Design optimisation · CPC title

  • G06F30/392Primary

    Floor-planning or layout, e.g. partitioning or placement · CPC title

  • Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

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What does patent US11036910B2 cover?
A method of designing a microwave filter using a computerized filter optimizer, comprises generating a filter circuit design in process (DIP) comprising a plurality of circuit elements having a plurality of resonant elements and one or more non-resonant elements, optimizing the DIP by inputting the DIP into the computerized filter optimizer, determining that one of the plurality of circuit elem…
Who is the assignee on this patent?
Resonant Inc
What technology area does this patent fall under?
Primary CPC classification H03H9/46. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 15 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).