Unified addressing and hierarchical heterogeneous storage and memory

Patent metadata

Field	Value
Publication number	US-11036397-B2
Application number	US-201916543511-A
Country	US
Kind code	B2
Filing date	Aug 16, 2019
Priority date	Aug 19, 2014
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

According to one general aspect, an apparatus may include a processor, a heterogeneous memory system, and a memory interconnect. The processor may be configured to perform a data access on data stored in a memory system. The heterogeneous memory system may include a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with one or more performance characteristics. The heterogeneous memory system may include both volatile and non-volatile storage mediums. The memory interconnect may be configured to route the data access from the processor to at least one of the storage mediums based, at least in part, upon the one or more performance characteristic associated with the respective memory technologies of the storage media.

First claim

What is claimed is:

1. An apparatus comprising:
a processor configured to perform a data access to a memory system;
a heterogeneous memory system comprising a plurality of storage mediums wherein each type of storage medium is based upon a respective memory technology and is associated with one or more physical performance characteristics; and
a memory interconnect configured to:
locally route the data access from the processor to a determined at least one target storage medium of the plurality of storage mediums based, at least in part, upon the one or more performance characteristics associated with the respective memory technologies of the storage mediums.

2. The apparatus of claim 1 , wherein the processor is configured to employ a unified access protocol regardless of the type of storage medium employed to store the data.

3. The apparatus of claim 2 , wherein the memory interconnect is configured to translate the data access from the unified access protocol employed by the processor to a storage medium specific protocol employed by a storage medium employed to store the data.

4. The apparatus of claim 1 , wherein the memory interconnect includes a system memory interface configured to receive data accesses to a first group of the plurality of storage mediums and a secondary storage interface configured to receive data accesses to a second group of the plurality of storage mediums.

5. The apparatus of claim 1 , the plurality of storage mediums includes storage mediums based upon three or more different types of storage mediums, wherein the types are selected from a group consisting essentially of:
Dynamic Random Access Memory (DRAM),
Resistive Random Access Memory (RRAM),
Phase change Random Access Memory (PRAM),
Magnetic Random Access Memory (MRAM),
NAND flash memory, and
magnetic storage.

6. The apparatus of claim 1 , wherein the memory interconnect is configured to organize the hierarchy of storage medium tiers into a layered caching memory system.

7. The apparatus of claim 6 , wherein the memory interconnect includes a cache organizer circuit configured to track the contents of each storage medium within the layered caching memory system, and indicate which, if any, storage mediums, include the data associated with the data access.

8. The apparatus of claim 7 , wherein the memory interconnect is configured to route the data accesses to a storage medium included within a fastest layer of the layered caching memory system that includes the data associated with the data access.

9. The apparatus of claim 8 , wherein the memory interconnect is configured to, if the fastest layer of the layered caching memory system that includes the data associated with the data access includes a volatile storage medium, mirror the data within a non-volatile layer of the layered caching memory system.

10. The apparatus of claim 1 , wherein the memory interconnect is configured to:
dynamically organize at least a portion of the plurality of storage mediums into a hierarchy of storage medium tiers based, at least in part upon, the one or more performance characteristics associated with each type of storage medium; and
wherein the memory interconnect is configured to dynamically organize the hierarchy of storage medium tiers such that:
the hierarchy of storage medium tiers is prioritized towards speed, when the apparatus is operating via a substantially unlimited power supply, and
the hierarchy of storage medium tiers is prioritized towards power savings, when the apparatus is operating via a limited power supply.

11. A method comprising:
receiving, from a processor, a data access for a heterogeneous memory system,
wherein the heterogeneous memory system comprises a plurality of types of storage mediums, and wherein the heterogeneous memory system, wherein each type of storage medium is associated with one or more performance characteristic;
determining, by a memory interconnect, a target storage medium of the heterogeneous memory system for the data access, wherein determining is based, at least in part, upon at least one performance characteristic associated with the target storage medium; and
locally routing, by the memory interconnect, the data access, at least partially, between the processor and the target storage medium.

12. The method of claim 11 , wherein the heterogeneous memory system comprises at least one volatile storage medium and at least one non-volatile storage medium; and
wherein determining comprises:
if the memory interconnect is operating via a substantially unlimited power supply, selecting the at least one volatile storage mediums as the target storage medium, and
if the memory interconnect is disconnected from the substantially unlimited power supply, selecting the at least one non-volatile storage mediums as the target storage medium.

13. The method of claim 11 , wherein receiving the data access includes receiving an indication of a data category associated with the data access; and
wherein routing includes preferentially routing the data to one of the plurality of types of storage mediums based upon the data category.

14. The method of claim 13 , wherein the data category associated with the data is set during a compilation of a software program that, when executed by the processor, causes the data access.

15. The method of claim 11 , further comprising organizing at least a portion of the plurality of types of storage mediums into a layered caching memory system based, at least in part upon, the one or more performance characteristic associated with each type of storage medium; and
wherein routing includes routing the data access to a storage medium included within a fastest layer of the layered caching memory system that includes the piece of data associated with the data access.

16. The method of claim 11 , further comprising:
organizing at least a portion of the plurality of types of storage mediums into a hierarchy of storage medium tiers; and
dynamically re-organizing the heterogeneous memory system in response to an at least partial failure of a compromised storage medium included by the heterogeneous memory system, wherein dynamically re-organizing includes reducing a usage of the compromised storage medium.

17. An apparatus comprising:
a processor interface configured to receive a data access;
at least one of storage medium interface, each configured to communicate with at least one storage medium of a heterogeneous memory system, and each storage medium interface being at least indirectly associated with at least one performance characteristic, herein the heterogeneous memory system comprises a plurality of types of storage mediums; and
a memory controller configured to locally route the data access from the processor interface to a one of the plurality of storage medium interfaces based, at least in part, upon at least one performance characteristic associated with the one of the plurality of storage medium interfaces.

18. The apparatus of claim 17 , further comprising a memory configured to store at least one set of storage preferences; and
wherein the memory controller is configured to select the one of the plurality of storage medium interfaces based, at least in part, upon the at least one performance characteristics associated with the plurality of storage medium interfaces and the storage preferences.

19. The apparatus of claim 18 , wherein the data access is associated with a data category; and
wherein the storage preferences dictate a priority of performance charact

Assignees

• Samsung Electronics Co Ltd

Inventors

• Haghighi Siamack
• Brennan Robert

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title