Pass through storage devices

Patent metadata

Field	Value
Publication number	US-2016011965-A1
Application number	US-201314028528-A
Country	US
Kind code	A1
Filing date	Sep 16, 2013
Priority date	Mar 15, 2013
Publication date	Jan 14, 2016
Grant date	—

Abstract

The disclosure is directed to apparatus and methods for implementing a pass through storage architecture that converts. Embodiments generally include a control circuit configured to allocate data among at least a first memory tier and a second memory tier. The first memory tier can include a solid state memory and the second memory tier can include a nonvolatile memory. In some embodiments, a pass-through storage device may be implemented. Embodiments may further include one or more interfaces configured to allow communication between the control circuit and one or more memories, devices, systems, or any combination thereof.

First claim

What is claimed is:

1 . An apparatus comprising:
a control circuit configured to allocate data among at least a first memory tier and a second memory tier, the first memory tier including a nonvolatile solid state memory and the second memory tier including another nonvolatile memory; a host interface configured to communicate between the control circuit and a host device; a data storage device interface configured to communicate between the control circuit and a data storage device that includes the second memory tier, the data storage device interface mimicking the host interface such that the data storage device interfaces with the apparatus as if the data storage device were interfacing directly with the host device; and the control circuit is further configured to manage transfer of data to the host device, the first memory tier, and the second memory tier.

2 . The apparatus of claim 1 further comprising the control circuit is integrated on the host device such that data can be transmitted among the host device, the first memory tier, and the second memory tier.

3 . The apparatus of claim 1 further comprising the control circuit is integrated on the data storage device that includes the nonvolatile memory of the second memory tier such that data can be transmitted among the host device, the first memory tier, and the second memory tier.

4 . The apparatus of claim 1 is a separately removable hardware device disconnectable from the host interface and the data storage device interface, the apparatus including the nonvolatile solid state memory configured as a buffer.

5 . The apparatus of claim 4 further comprising a nonvolatile solid state memory protocol processor configured to, when data is allocated to the nonvolatile solid state memory, implement a protocol translation layer that translates the allocated data such that the allocated data is in a format readable by the nonvolatile solid state memory.

6 . The apparatus of claim 5 further comprising:
a buffer manager configured to communicate with the control circuit and allocate data among one or more volatile memory units configured as a buffer; and
a first-in-first-out (FIFO) memory unit configured to store data received from the buffer manager and transmit the received data to the nonvolatile solid state memory protocol processor.

7 . The apparatus of claim 5 , the nonvolatile solid state memory is Flash memory and the nonvolatile memory is a magnetic data storage medium, the apparatus further comprising a buffer manager configured to communicate with the control circuit and allocate data among one or more volatile memory units configured as a buffer.

8 . The apparatus of claim 5 further comprising:
the first memory tier; and
an output from the nonvolatile solid state memory protocol processor, the output configured to couple the nonvolatile solid state memory protocol processor to the nonvolatile solid state memory.

9 . The apparatus of claim 5 further comprising a nonvolatile solid state memory interface configured to communicate between the nonvolatile solid state memory protocol processor and the nonvolatile solid state memory, the first memory tier is integrated on one or more separately removable hardware devices disconnectable from the apparatus.

10 . The apparatus of claim 1 further comprising:
the control circuit is further configured to:
cache data in the nonvolatile solid state memory of the first memory tier for data that meets one or more cache criteria; and
store data in the nonvolatile memory of the second tier at least in part as storage space for data that meets one or more storage criteria for the second memory tier.

11 . The apparatus of claim 10 further comprising the one or more cache criteria and the one or more storage criteria are determined based on one or more parameters selected from a group consisting of: timing, capacity, power event, and idle time.

12 . An apparatus comprising:
a control circuit configured to allocate data among at least a first memory tier and a second memory tier, the first memory tier including a nonvolatile solid state memory and the second memory tier including another nonvolatile memory; an initiator interface configured to communicate between the control circuit and an initiator device; a target interface configured to communicate between the control circuit and a target device; at least one of the initiator interface and the target interface replicates a host interface such that a data storage device including the nonvolatile memory of the second memory tier interfaces with the apparatus as if it were interfacing with a host device; and the control circuit is further configured to manage transfer of data to the host device, the first memory tier, and the second memory tier.

13 . The apparatus of claim 12 further comprising the initiator interface and the target interface are each compliant to an interface standard.

14 . The apparatus of claim 12 further comprising the control circuit is configured to cache all data to the nonvolatile solid state memory of the first memory tier before storing the data to the nonvolatile memory of the second memory tier.

15 . The apparatus of claim 14 further comprising a buffer manager configured to communicate with the control circuit and allocate data among one or more volatile memory units configured as a buffer.

16 . The apparatus of claim 15 further comprising a nonvolatile solid state memory protocol processor configured to, when data is allocated to the nonvolatile solid state memory, implement a protocol translation layer that translates the allocated data such that the allocated data is in a format readable by the nonvolatile solid state memory.

17 . The apparatus of claim 16 further comprising:
a nonvolatile solid state memory interface configured to communicate between the nonvolatile solid state memory protocol processor and the nonvolatile solid state memory; and
a volatile memory interface configured to communicate between the buffer manager and one or more volatile memory units configured as a buffer.

18 . An apparatus comprising:
a control circuit configured to:
receive, from a host system, a request to write selected data;
cache the selected data to a first nonvolatile solid state memory; and
store at least a subset of the selected data to a second nonvolatile memory based on a trigger event;
a host interface configured to communicate between the control circuit and the host system; and a data storage interface configured to communicate between the control circuit and the second nonvolatile memory, the data storage interface mimicking the host interface such that the data storage device interfaces with the apparatus as if the data storage device were interfacing directly with the host system.

19 . The apparatus of claim 18 , the selected data is translated by a protocol processor before it is cached to the first nonvolatile solid state memory such that the selected data is in a format readable by the first nonvolatile solid state memory.

20 . The apparatus of claim 19 further comprising a nonvolatile solid state memory interface configured to communicate between the protocol processor and the first nonvolatile solid state memory.

Assignees

• Seagate Technology Llc

Inventors

• Murphy Robert Dale
• Moon John Edward
• Keeler Stanton
• Bohn Richard Esten

Classifications

• G06F12/0868 Primary

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/126

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title