Low power chip-to-chip bidirectional communications

Patent metadata

Field	Value
Publication number	US-11032110-B2
Application number	US-202016808252-A
Country	US
Kind code	B2
Filing date	Mar 3, 2020
Priority date	Jun 28, 2017
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.

First claim

I claim:

1. A method comprising:
receiving, at a receiver, symbols of a codeword, the symbols received via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix;
generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC receiving a corresponding subset of the symbols of the codeword and having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, each comparator output indicative of the weight applied to the corresponding sub-channel vector;
outputting a set of forward-channel output bits formed based on the plurality of comparator outputs; and
generating a sequence of bits of a secondary data link carried by common-mode sub-channel constituent codewords using a common-mode MIC receiving all symbols of the codeword and having input coefficients associated with the common-mode sub-channel vector.

2. The method of claim 1 , further comprising obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode sub-channel constituent codewords over the wires of the multi-wire bus, each common-mode sub-channel constituent codeword transmitted by modulating weights of the common-mode sub-channel vector according to a corresponding bit in the sequence of reverse-channel bits.

3. The method of claim 2 , wherein the sequence of reverse-channel bits is transmitted in a time interval when the sequence of bits of the secondary data link is not being generated.

4. The method of claim 1 , wherein the sequence of bits of the secondary data link are generated at a rate that is less than a rate of the forward-channel output bits.

5. The method of claim 4 , wherein the rate of the sequence of bits of the secondary data link is 256 times slower than the rate of the forward-channel output bits.

6. The method of claim 1 , further comprising de-serializing the sequence of bits of the secondary data link.

7. The method of claim 1 , wherein the sequence of bits of the secondary data link are associated with messages selected from the group consisting of: command messages, error information messages, and management information messages.

8. The method of claim 1 , wherein the orthogonal matrix is represented by M:

M
=

1

1

1

1

1

1

1

-
1

0

0

0

0

1
/
2

1
/
2

-
1

0

0

0

0

0

0

1

-
1

0

0

0

0

1
/
2

1
/
2

-
1

1
/
3

1
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3

1
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3

-
1

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3

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1

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3

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1

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3.

9. The method of claim 1 , wherein the common-mode sub-channel constituent codewords are associated with a modulation of a baseline voltage of the wires of the multi-wire bus.

10. The method of claim 1 , wherein the common-mode sub-channel constituent codewords are generated by a transmitter sourcing and sinking current into the wires of the multi-wire bus.

11. An apparatus comprising:
a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant configured to:
receive symbols of a codeword, the symbols received via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix; and
generate a plurality of comparator outp

Assignees

• Kandou Labs SA

Inventors

• Hormati Ali

Classifications

• H04W72/23

  in the downlink direction of a wireless link, i.e. towards a terminal · CPC title

• H01Q13/24

  constituted by a dielectric or ferromagnetic rod or pipe (H01Q13/28 takes precedence) · CPC title

• H04L25/14

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title

• H04B3/14

  characterised by the equalising network used · CPC title

• H04L25/0292 Primary

  Arrangements specific to the receiver end · CPC title