Method of forming oxygen inserted Si-layers in power semiconductor devices

US11031466B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11031466-B2
Application numberUS-202016896593-A
CountryUS
Kind codeB2
Filing dateJun 9, 2020
Priority dateAug 8, 2018
Publication dateJun 8, 2021
Grant dateJun 8, 2021

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method of manufacturing a semiconductor device includes: forming one or more device epitaxial layers over a main surface of a doped Si base substrate; forming a diffusion barrier structure including alternating layers of Si and oxygen-doped Si in an upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate, in a lower part of the one or more device epitaxial layers adjacent the main surface of the doped Si base substrate, or in one or more additional epitaxial layers disposed between the main surface of the doped Si base substrate and the one or more device epitaxial layers; and forming a gate above the diffusion barrier structure.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing a semiconductor device, the method comprising: forming one or more device epitaxial layers over a main surface of a doped Si base substrate; forming a diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si in an upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate, in a lower part of the one or more device epitaxial layers adjacent the main surface of the doped Si base substrate, or in one or more additional epitaxial layers disposed between the main surface of the doped Si base substrate and the one or more device epitaxial layers; and forming a gate above the diffusion barrier structure. 2. The method of claim 1 , wherein forming the diffusion barrier structure comprises: forming the alternating layers of Si and oxygen-doped Si in the upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate. 3. The method of claim 1 , wherein forming the diffusion barrier structure comprises: forming the alternating layers of Si and oxygen-doped Si in the lower part of the one or more device epitaxial layers adjacent the main surface of the doped Si base substrate. 4. The method of claim 1 , wherein forming the diffusion barrier structure comprises: forming the alternating layers of Si and oxygen-doped Si in the one or more additional epitaxial layers disposed between the main surface of the doped Si base substrate and the one or more device epitaxial layers. 5. The method of claim 1 , further comprising: forming one or more gaps in the diffusion barrier structure. 6. The method of claim 5 , wherein forming the one or more gaps in the diffusion barrier structure comprises: forming a mask with one or more openings on the diffusion barrier structure; and etching the one or more gaps into the diffusion barrier structure through the one or more openings in the mask. 7. The method of claim 1 , further comprising: forming an additional diffusion barrier structure in the one or more device epitaxial layers and vertically spaced apart from the diffusion barrier structure, the additional diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si. 8. The method of claim 7 , further comprising: forming one or more gaps in the diffusion barrier structure and the additional diffusion barrier structure. 9. The method of claim 1 , further comprising: forming a drift zone formed in the one or more device epitaxial layers; forming a body region in the one or more device epitaxial layers above the drift zone and including a channel region; forming a source region in the one or more device epitaxial layers above the body region; and forming a contact trench in the one or more device epitaxial layers, the contact trench being filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench, wherein the diffusion barrier structure has a gap in the drift zone. 10. The method of claim 9 , further comprising: forming an additional diffusion barrier structure in the one or more device epitaxial layers and vertically spaced apart from the diffusion barrier structure, the additional diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si, wherein the gate is disposed in a gate trench formed above the diffusion barrier structure in the one or more device epitaxial layers and extending in a direction toward the main surface of the doped Si base substrate. 11. The method of claim 1 , further comprising: forming the diffusion barrier structure at an angle with respect to the main surface of the doped Si base substrate. 12. The method of claim 11 , wherein forming the diffusion barrier structure at the angle with respect to the main surface of the doped Si base substrate comprises: forming the diffusion barrier structure on an undulated surface of an epitaxial layer. 13. The method of claim 1 , wherein forming the gate comprises: insulating a planar gate from a main surface of the one or more device epitaxial layers by a gate dielectric. 14. The method of claim 1 , wherein forming the diffusion barrier structure comprises: forming a Si buffer layer below the alternating layers of Si and oxygen-doped Si. 15. The method of claim 1 , wherein forming the diffusion barrier structure comprises: forming a capping layer of Si on the alternating layers of Si and oxygen-doped Si. 16. The method of claim 1 , wherein forming the diffusion barrier structure comprises: forming a Si buffer layer below the alternating layers of Si and oxygen-doped Si; and forming a capping layer of Si on the alternating layers of Si and oxygen-doped Si. 17. The method of claim 1 , wherein the alternating layers of Si and oxygen-doped Si are formed by Si epitaxy with absorption of oxygen at different steps. 18. The method of claim 17 , further comprising: controlling temperature and gaseous conditions during the Si epitaxy to form partial oxygen monolayers as the layers of oxygen-doped Si. 19. The method of claim 1 , further comprising: etching a plurality of trenches into the diffusion barrier structure. 20. The method of claim 19 , further comprising: forming a lateral gap between the trenches and the diffusion barrier structure such that the diffusion barrier structure is laterally spaced apart from the trenches.

Assignees

Inventors

Classifications

  • by ion implantation · CPC title

  • being group IV material · CPC title

  • Delta-doping · CPC title

  • Silicon, silicon germanium or germanium · CPC title

  • Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11031466B2 cover?
A method of manufacturing a semiconductor device includes: forming one or more device epitaxial layers over a main surface of a doped Si base substrate; forming a diffusion barrier structure including alternating layers of Si and oxygen-doped Si in an upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate, in a lower part of the one or more device epi…
Who is the assignee on this patent?
Infineon Technologies Austria Ag, Infineon Technologies Americas Corp
What technology area does this patent fall under?
Primary CPC classification H10D30/668. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 08 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).