Low resistance high capacitance density MIM capacitor

Patent metadata

Field	Value
Publication number	US-11031457-B2
Application number	US-201715843145-A
Country	US
Kind code	B2
Filing date	Dec 15, 2017
Priority date	Dec 15, 2017
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Embodiments are directed to a method and resulting structures for forming low resistance, high capacitance density MIM capacitors. In a non-limiting embodiment, one or more bottom plate contacts are formed over a substrate. A bottom capacitor plate is formed directly on a top surface and a sidewall of each of the one or more bottom plate contacts. A capacitor dielectric layer is formed directly on a surface of the bottom capacitor plate. A top capacitor plate is formed directly on a surface of the capacitor dielectric layer. A first portion of the top capacitor plate extends past a sidewall of the bottom capacitor plate in a direction parallel to the substrate. A top plate contact is formed directly on the first portion of the top capacitor plate.

First claim

What is claimed is:

1. A method for forming a semiconductor device, the method comprising:
forming one or more bottom plate contacts including a barrier metal liner with a high electrical conductivity over a substrate;
forming a bottom capacitor plate directly on a top surface and a sidewall of each of the one or more bottom plate contacts, wherein a sidewall of the bottom capacitor plate is in direct contact with an entirety of a sidewall of one bottom plate contact of the one or more bottom plate contacts;
forming a capacitor dielectric layer directly on a surface of the bottom capacitor plate, a first portion of the capacitor dielectric layer extending in a direction parallel to the substrate and remaining above a highest portion of the one or more bottom plate contacts forming an offset region;
forming a top capacitor plate directly on a surface of the capacitor dielectric layer, a first portion of the top capacitor plate extending above the offset region; and
forming a top plate contact directly on the first portion of the top capacitor plate so as not to overlay a portion of the bottom capacitor plate in the offset region, wherein the one bottom plate contact of the one or more bottom plate contacts has a top surface in direct contract with the bottom capacitor plate and a bottom surface in direct contact with the substrate, the one bottom plate contact having an entirety of another sidewall in direct contact with dielectric material, the another sidewall and the sidewall of the one bottom plate contact being opposite one another.

2. The method of claim 1 , wherein the one or more bottom plate contacts comprise a line width of greater than or equal to about 0.1 microns.

3. The method of claim 1 , wherein the one or more bottom plate contacts comprise a material selected from the group consisting of tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, and gold.

4. The method of claim 1 , wherein the capacitor dielectric layer comprises a high-k dielectric material comprising a dielectric constant greater than 7.0.

5. The method of claim 4 , wherein the high-k dielectric material is selected from the group consisting of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

6. The method of claim 1 further comprising, prior to forming the bottom capacitor plate, forming a hard mask over a first region of the substrate.

7. The method of claim 6 further comprising removing portions of an interlayer dielectric in a second region of the substrate that is not covered by the hard mask.

8. The method of claim 7 further comprising recessing a height of the one or more bottom plate contacts in the second region of the substrate.

9. A semiconductor device comprising:
one or more bottom plate contacts including a barrier metal liner with a high electrical conductivity formed over a substrate;
a bottom capacitor plate formed directly on a top surface and a sidewall of each of the one or more bottom plate contacts, wherein a sidewall of the bottom capacitor plate is in direct contact with an entirety of a sidewall of one bottom plate contact of the one or more bottom plate contacts;
a capacitor dielectric layer formed directly on a surface of the bottom capacitor plate, a first portion of the capacitor dielectric layer extending in a direction parallel to the substrate and remaining above a highest portion of the one or more bottom plate contacts forming an offset region;
a top capacitor plate formed directly on a surface of the capacitor dielectric layer, a first portion of the top capacitor plate extending above the offset region; and
a top plate contact formed directly on the first portion of the top capacitor plate so as not to overlay a portion of the bottom capacitor plate in the offset region, wherein the one bottom plate contact of the one or more bottom plate contacts has a top surface in direct contract with the bottom capacitor plate and a bottom surface in direct contact with the substrate, the one bottom plate contact having an entirely of another sidewall in direct contact with dielectric material, the another sidewall and the sidewall of the one bottom plate contact being opposite one another.

10. The semiconductor device of claim 9 , wherein the one or more bottom plate contacts comprise a line width of greater than or equal to about 0.1 microns.

11. The semiconductor device of claim 9 , wherein the one or more bottom plate contacts comprise a material selected from the group consisting of tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, and gold.

12. The semiconductor device of claim 9 , wherein the capacitor dielectric layer comprises a high-k dielectric material comprising a dielectric constant greater than 7.0.

13. The semiconductor device of claim 12 , wherein the high-k dielectric material is selected from the group consisting of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

14. The method of claim 1 , wherein no portion of the bottom capacitor plate is immediately under the top plate contact in the offset region.

15. The method of claim 1 , wherein the sidewall of the bottom capacitor plate is coplanar with the sidewall of the one or more bottom plate contacts; and
wherein a sidewall of the top plate contact is coplanar with a sidewall of the top capacitor plate.

16. The method of claim 1 , wherein a bottom surface of the bottom capacitor plate is directly on the substrate.

17. The method of claim 1 , wherein the dielectric material extends from the one bottom plate contact to a side surface of the top plate contact.

Assignees

• IBM

Inventors

• Li Baozhen
• Yang Chih-Chao

Classifications

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title

• H10D1/714

  having horizontal extensions · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/68

  Capacitors having no potential barriers · CPC title