MIM capacitor structure

Patent metadata

Field	Value
Publication number	US-9368392-B2
Application number	US-201414249498-A
Country	US
Kind code	B2
Filing date	Apr 10, 2014
Priority date	Apr 10, 2014
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer.

First claim

What is claimed is:

1. A MIM (metal-insulator-metal) capacitor, comprising:
a first electrode comprising a bottom capacitor metal layer;
a capacitor dielectric layer disposed onto and in direct contact with the bottom capacitor metal layer;
a second electrode comprising a top capacitor metal layer disposed onto and in direct contact with the capacitor dielectric layer;
a third electrode comprising a middle capacitor metal layer, separated from the top capacitor metal layer by a second capacitor dielectric layer;
a capacitor inter-level dielectric (ILD) layer disposed over the top capacitor metal layer;
a substantially planar etch stop layer disposed over the capacitor ILD layer;
a plurality of vias extending through the capacitor ILD layer to the first electrode and the second electrode; and
a plurality of metal wires overlying the plurality of vias, wherein the plurality of metal wires extend through the etch stop layer and have a greater width than the plurality of vias at an interface between the plurality of metal wires and the plurality of vias.

2. The MIM capacitor of claim 1 , wherein the middle capacitor metal layer extends beyond the top capacitor metal layer on opposing sides.

3. The MIM capacitor of claim 1 , wherein the plurality of vias comprise:
a first via vertically extending through the capacitor dielectric layer to a first position that electrically contacts the bottom capacitor metal layer;
a second via vertically extending through the second capacitor dielectric layer to a second position that electrically contacts the middle capacitor metal layer; and
a third via vertically extending through the capacitor ILD layer to a third position that electrically contacts the top capacitor metal layer.

4. The MIM capacitor of claim 1 , wherein the bottom capacitor metal layer, the middle capacitor metal layer, and the top capacitor metal layer have a thickness that is between approximately 100 angstrom and approximately 800 angstrom.

5. The MIM capacitor of claim 1 , wherein the capacitor dielectric layer comprises one or more of the following: silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), tantalum oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), strontium titanate (SrTiO 3 ), zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), hafnium silicate (HfSiO 4 ), lanthanum oxide (La 2 O 3 ), or yttrium oxide (Y 2 O 3 ).

6. The MIM capacitor of claim 1 , wherein the bottom capacitor metal layer is disposed onto and in direct contact with a dielectric buffer layer located over an under-metal layer comprising one or more metal structures located under the bottom capacitor metal layer.

7. The MIM capacitor of claim 1 , wherein the third electrode is separated from a first via contacting the first electrode and is further separated from a second via contacting the second electrode, and wherein the first via and the second via are different vias.

8. The MIM capacitor of claim 1 , wherein the third electrode is not in contact with an underlying or an overlying via.

9. The MIM capacitor of claim 1 , further comprising: a dielectric buffer layer located over an under-metal layer comprising one or more metal structures located under the bottom capacitor metal layer, wherein the capacitor dielectric layer continuously extends from a location in contact with the dielectric buffer layer to locations vertically between the first electrode and second electrode and vertically between the second electrode and the third electrode.

10. The MIM capacitor of claim 1 , wherein the capacitor dielectric layer and the third electrode are laterally located between segments of the first electrode.

11. The MIM capacitor of claim 1 , wherein the capacitor dielectric layer is laterally arranged between parts of the first electrode.

12. The MIM capacitor of claim 3 , wherein the first via, the second via, and the third via, respectively contact the bottom capacitor metal layer, the middle capacitor metal layer and the top capacitor metal layer at a substantially same vertical position.

13. The MIM capacitor of claim 6 , wherein the bottom capacitor metal layer extends beyond the top capacitor metal layer on opposing sides to form a stepped pyramid structure having steps that recede in size as a distance from the dielectric buffer layer increases.

14. A MIM (metal-insulator-metal) capacitor, comprising:
a first electrode comprising a bottom capacitor metal layer disposed onto and in direct contact with a dielectric buffer layer disposed over an under-metal layer comprising one or more metal structures located under the bottom capacitor metal layer;
a second electrode comprising a middle capacitor metal layer separated from the bottom capacitor metal layer by a first capacitor dielectric layer disposed onto and in direct contact with the bottom capacitor metal layer;
a third electrode comprising a top capacitor metal layer separated from the middle capacitor metal layer by a second capacitor dielectric layer disposed onto and in direct contact with the middle capacitor metal layer;
a capacitor inter-level dielectric (ILD) layer disposed over the top capacitor metal layer;
a substantially planar etch stop layer disposed over the capacitor ILD layer; and
wherein the bottom capacitor metal layer extends beyond the middle capacitor metal layer on opposing sides and the middle capacitor metal layer extends beyond the top capacitor metal layer on opposing sides, so as to form a stepped pyramid structure having steps that recede in size as a distance from the dielectric buffer layer increases.

15. The MIM capacitor of claim 14 , further comprising:
a first via vertically extending through the first capacitor dielectric layer to a first position that electrically contacts the bottom capacitor metal layer;
a second via vertically extending through the second capacitor dielectric layer to a second position that electrically contacts the middle capacitor metal layer; and
a third via vertically extending through the capacitor ILD layer to a third position that electrically contacts the top capacitor metal layer.

16. The MIM capacitor of claim 15 , wherein the first via, the second via, and the third via, respectively contact the bottom capacitor metal layer, the middle capacitor metal layer and the top capacitor metal layer at a substantially same vertical position.

17. A method of forming an integrated chip having a MIM (metal-insulator-metal) capacitor, comprising:
forming a bottom capacitor metal layer at a position that is in direct contact with a dielectric buffer layer disposed over an under-metal layer comprising one or more metal structures located under the bottom capacitor metal layer;
forming a capacitor dielectric layer onto and in contact with the bottom capacitor metal layer;
forming a top capacitor metal layer over the capacitor dielectric layer;
forming a capacitor inter-level dielectric (ILD) layer over the top capacitor metal layer;
performing a planarization process on the capacitor ILD layer to form a substantially planar ILD surface;
forming a substantially planar etch stop layer disposed over the capacitor ILD layer; and
forming a first via hole that vertically extends through the capacitor ILD layer to a first position that electrically contacts the bottom capacitor metal layer and a second via hole that vertically extends through the capacitor ILD layer to a second position that electrically contacts the top capacitor metal layer, wherein the first via hole and the second via hole extend to a same vertical position.

1

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tseng Wei-Min
• Shen Shih-Guo
• Wang Chien-Chung
• Chu Huey-Chi
• Chiang Wen-Chuan

Classifications

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/081 Primary

  by forming openings in the dielectric parts · CPC title

• H10D84/212 Primary

  of only capacitors · CPC title