Array substrate, method for manufacturing the same, and display device

Patent metadata

Field	Value
Publication number	US-11031419-B2
Application number	US-201916382679-A
Country	US
Kind code	B2
Filing date	Apr 12, 2019
Priority date	Sep 17, 2018
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a base substrate and the array substrate includes a plurality of pixel units. In each of the plurality of pixel units, the array substrate includes a thin film transistor and a storage capacitor disposed above the base substrate, the storage capacitor includes a metal layer, an intermediate layer, and a reflective layer disposed in a stacked manner, the metal layer being adjacent to the base substrate. The array substrate further includes a common electrode layer disposed on a side of the storage capacitor facing away from the base substrate, the reflective layer is electrically connected to the common electrode layer, and the metal layer is electrically connected to an active layer of the thin film transistor.

First claim

What is claimed is:

1. An array substrate, comprising a base substrate, wherein the array substrate comprises a plurality of pixel units,
wherein, in each of the plurality of pixel units, the array substrate comprises a thin film transistor and a storage capacitor disposed above the base substrate,
wherein the storage capacitor comprises a metal layer, an intermediate layer, and a reflective layer disposed in a stacked manner, the metal layer being adjacent to the base substrate,
wherein the array substrate further comprises a common electrode layer disposed on a side of the storage capacitor facing away from the base substrate, the reflective layer is electrically connected to the common electrode layer, and the metal layer is electrically connected to an active layer of the thin film transistor;
wherein the thin film transistor comprises the active layer, a gate insulating layer, a gate electrode layer, an interlayer dielectric layer and a source-drain metal layer stacked sequentially on a side of the base substrate, and the active layer is adjacent to the base substrate; and
wherein the gate electrode layer and the metal layer are formed by using one and the same mask, the interlayer dielectric layer serves as the intermediate layer of the storage capacitor, and the metal layer is electrically connected to the active layer through a via hole provided in the gate insulating layer.

2. The array substrate according to claim 1 , wherein the array substrate further comprises a planarization layer disposed between the storage capacitor and the common electrode layer, and the common electrode layer is electrically connected to the reflective layer through a via hole provided in the planarization layer.

3. The array substrate according to claim 1 , wherein the array substrate further comprises a passivation layer and a pixel electrode layer disposed on a side of the common electrode layer facing away from the base substrate, and the pixel electrode layer is electrically connected to the thin film transistor through a via hole provided in the passivation layer.

4. The array substrate according to claim 1 , wherein the reflective layer is made of silver material.

5. The array substrate according to claim 1 , wherein the thin film transistor comprises a gate electrode layer, a gate insulating layer, the active layer, and a source-drain metal layer stacked sequentially on a side of the base substrate.

6. The array substrate according to claim 1 , wherein the active layer comprises a channel region and a conduction region, the metal layer is electrically connected to the conduction region of the active layer, and the source-drain metal layer is electrically connected to the conduction region of the active layer.

7. The array substrate according to claim 6 , wherein an orthographic projection of the gate electrode layer on the base substrate covers an orthographic projection of the channel region on the base substrate.

8. The array substrate according to claim 1 , wherein the active layer of the thin film transistor is made of a low temperature polysilicon material.

9. A display device, comprising the array substrate according to claim 1 .

10. A method for manufacturing an array substrate, comprising:
providing a base substrate;
forming a thin film transistor and a storage capacitor above the base substrate, the storage capacitor comprising a metal layer, an intermediate layer, and a reflective layer sequentially formed above the base substrate, the metal layer being electrically connected to an active layer of the thin film transistor;
forming a common electrode layer on a side of the storage capacitor facing away from the base substrate, the reflective layer being electrically connected to the common electrode layer;
wherein the forming a thin film transistor and a storage capacitor above the base substrate comprises:
forming the active layer, a gate insulating layer, a gate electrode layer, an interlayer dielectric layer, and a source-drain metal layer on a side of the base substrate sequentially; and
wherein the metal layer and the gate electrode layer are formed by using one and the same mask, the interlayer dielectric layer serves as the intermediate layer of the storage capacitor, and the metal layer is electrically connected to the active layer through a via hole provided in the gate insulating layer.

11. The method according to claim 10 , wherein, before the forming a common electrode layer on a side of the storage capacitor facing away from the base substrate, the method further comprises:
forming a planarization layer on the side of the storage capacitor facing away from the base substrate,
wherein the common electrode layer is formed on a side of the planarization layer facing away from the base substrate, and the common electrode layer is electrically connected to the reflective layer through a via hole provided in the planarization layer.

12. The method according to claim 10 , wherein the method further comprises:
forming a passivation layer and a pixel electrode layer on a side of the common electrode layer facing away from the base substrate sequentially, the pixel electrode layer being electrically connected to the thin film transistor through a via hole provided in the passivation layer.

Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Xue Jinjin
• Shi Dawei
• Li Feng
• Yao Lei
• Wang Wentao
• Xu Haifeng
• Yang Lu
• Hou Lin
• Wang Jinfeng
• Li Mei
• Fang Yezhou

Classifications

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/481 Primary

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• G02F2202/104

  poly-Si · CPC title