Integrated circuit package and method of forming same

Patent metadata

Field	Value
Publication number	US-11031345-B2
Application number	US-201916536633-A
Country	US
Kind code	B2
Filing date	Aug 9, 2019
Priority date	Aug 14, 2018
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer, a die disposed in a cavity of the core layer, and an encapsulant disposed in the cavity between the die and a sidewall of the cavity. The package further includes a first patterned conductive layer disposed within the first dielectric layer, a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, a second patterned conductive layer disposed within the second dielectric layer, and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is between the conductive pad and the core layer.

First claim

What is claimed is:

1. An integrated circuit package, comprising:
a substrate comprising a core layer disposed between a first dielectric layer and a second dielectric layer;
a die disposed in a cavity of the core layer;
an encapsulant disposed in the cavity between the die and a sidewall of the cavity;
a first patterned conductive layer disposed within the first dielectric layer;
a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, wherein the device is electrically connected to the die;
a second patterned conductive layer disposed within the second dielectric layer; and
a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is between the conductive pad and the core layer, wherein the conductive pad is electrically connected to the die; and
a field plate disposed within the first dielectric layer, wherein the field plate is spaced apart from the die.

2. The package of claim 1 , wherein the field plate is electrically connected to a second conductive pad disposed on the outer surface of the second dielectric layer.

3. The package of claim 1 , wherein the die further comprises a field termination structure disposed on an outer surface of the die that faces the field plate, wherein at least a portion of the field plate overlaps the field termination structure in a direction orthogonal to the outer surface of the first dielectric layer.

4. The package of claim 1 , wherein the first and second dielectric layers are laminated to the substrate.

5. The package of claim 1 , wherein the encapsulant comprises a portion of the first dielectric layer.

6. The package of claim 1 , wherein the die comprises a high voltage electrical component.

7. The package of claim 6 , wherein the high voltage electrical component is operable with a potential of at least 500 volts.

8. The package of claim 1 , wherein the die comprises at least one of a field effect transistor, a metal oxide semiconductor field effect transistor, an insulated gate bipolar junction transistor, a thyristor, a bipolar transistor, a diode, a MOS-controlled thyristor, a resistor, and a capacitor.

9. The package of claim 1 , wherein each of the first and second dielectric layers comprises two or more sublayers that are laminated together.

10. The package of claim 9 , wherein the first patterned conductive layer is disposed between two sublayers of the first dielectric layer.

11. The package of claim 9 , wherein the second patterned conductive layer is disposed between two sublayers of the second dielectric layer.

12. An implantable medical device comprising the integrated circuit package of claim 1 .

Assignees

• Medtronic Inc

Inventors

• Kim Chunho
• Boone Mark R
• Crutchfield Randolph E

Classifications

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W90/00

  Package configurations · CPC title