Side mounted interconnect bridges

Patent metadata

Field	Value
Publication number	US-11031341-B2
Application number	US-201716474005-A
Country	US
Kind code	B2
Filing date	Mar 29, 2017
Priority date	Mar 29, 2017
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

A device and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a substrate;
a motherboard attached to the substrate;
a first semiconductor die attached to the substrate, wherein the substrate includes multi-layer break out pads;
a silicon interconnect bridge attached to a side surface of the substrate and wherein the silicon interconnect bridge is electrically coupled to the first semiconductor die via the multi-layer break out pads;
a second semiconductor die electrically coupled to a second end of the silicon interconnect bridge, wherein the second semiconductor die is attached to the motherboard and wherein the motherboard includes a cavity;
wherein the second end of the interconnect bridge extends into the cavity of the motherboard;
wherein the silicon interconnect bridge is attached to the motherboard within the cavity of the motherboard; and
wherein the silicon interconnect bridge is electrically coupled to the second semiconductor die via the motherboard.

2. The semiconductor device of claim 1 , wherein the second semiconductor die is a memory die.

3. The semiconductor device of claim 1 , wherein the first semiconductor die is a central processing unit.

4. The semiconductor device of claim 1 , wherein the interconnect bridge is attached to the substrate orthogonal to the first semiconductor die.

5. A computing device, comprising:
a mass storage device;
a substrate;
a motherboard attached to the substrate;
a first semiconductor die attached to a top surface of the substrate, wherein the substrate includes multi-layer break out pads;
a silicon interconnect bridge attached to a side surface of the substrate, the side surface orthogonal to the top surface, and wherein a first end of the silicon interconnect bridge is electrically coupled to the first semiconductor die via the multi-layer break out pads; and
a second semiconductor die electrically coupled to a second end of the silicon interconnect bridge, wherein the second semiconductor die is attached to the motherboard and wherein the motherboard includes a cavity;
wherein the second end of the interconnect bridge extends into the cavity of the motherboard;
wherein the silicon interconnect bridge is attached to the motherboard within the cavity of the motherboard; and
wherein the silicon interconnect bridge is electrically coupled to the second semiconductor die via the motherboard.

6. The semiconductor device of claim 5 , wherein the computing device is a cellular telephone.

7. A method comprising:
attaching a first semiconductor die to a top surface of a substrate;
attaching a first end of a silicon interconnect, bridge to a side surface of the substrate using a set of multi-layer break out pads of the substrate, wherein the first end of the silicon interconnect bridge is electrically coupled to the first semiconductor die; and
coupling, electrically, a second semiconductor die to a second end of the interconnect bridge;
attaching a bottom surface of the substrate to a motherboard, wherein the motherboard includes a cavity;
wherein the second end of the interconnect bridge extends into the cavity; and
wherein coupling the second semiconductor die to the second end of the interconnect bridge includes attaching the second end of the interconnect bridge to the motherboard with the cavity.

Assignees

• Intel Corp
• Hossain Md Altai
• Doran Kevin J
• Zhang Yu Amos
• Qian Zhiguo

Inventors

• Hossain Md Altai
• Doran Kevin J
• Zhang Yu Amos
• Qian Zhiguo

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/657

  on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers · CPC title