Passive components in vias in a stacked integrated circuit package

Patent metadata

Field	Value
Publication number	US-11031288-B2
Application number	US-201916252420-A
Country	US
Kind code	B2
Filing date	Jan 18, 2019
Priority date	Dec 24, 2014
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

Integrated passive components in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die including a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.

First claim

The invention claimed is:

1. A method comprising:
forming a plurality of vias in a silicon wafer;
forming passive devices in a portion of the plurality of vias, wherein forming passive devices in the portion of the plurality of vias comprises forming a capacitor in one of the plurality of vias;
forming power supply circuits on the silicon wafer from the passive devices after forming the passive devices;
dicing the silicon wafer to produce a plurality of uncore dies each having a power supply circuit;
attaching one of the plurality of uncore dies to a substrate; and
attaching a cores die having a processing core to the uncore die, the cores die over the uncore die, the cores die being coupled to the power supply circuit through the passive devices of the uncore die to power the processing core.

2. The method of claim 1 , further comprising overmolding the one of the plurality of uncore dies and the substrate with a molding compound or encapsulant.

3. The method of claim 1 , wherein forming passive devices in the portion of the plurality of vias comprises forming an inductor in one of the plurality of vias.

4. A method comprising:
forming a plurality of vias in a silicon wafer;
forming passive devices in or on the silicon wafer, wherein forming passive devices in or on the silicon wafer comprises forming a capacitor in or on the silicon wafer;
forming power supply circuits on the silicon wafer from the passive devices;
dicing the silicon wafer to produce a plurality of uncore dies each having a power supply circuit;
attaching one of the plurality of uncore dies to a substrate; and
attaching a cores die having a processing core to the uncore die, the cores die over the uncore die, the cores die being coupled to the power supply circuit through the passive devices of the uncore die to power the processing core.

5. The method of claim 4 , further comprising:
forming a capacitor in the cores die; and
coupling the capacitor to the power supply circuit.

6. The method of claim 4 , wherein forming passive devices in or on the silicon wafer comprises forming an inductor in or on the silicon wafer.

7. The method of claim 6 , wherein forming the inductor in or on the silicon wafer comprises forming a recess in the silicon wafer, and forming a magnetic inductor in the recess.

8. The method of claim 7 , wherein forming the recess comprises forming a recess having a bottom and angled sidewalls.

9. The method of claim 8 , wherein forming the magnetic inductor in the recess comprises forming only a portion of the magnetic inductor in the recess.

10. The method of claim 7 , wherein forming the recess comprises forming a recess having a bottom and vertical sidewalls.

11. The method of claim 10 , wherein forming the magnetic inductor in the recess comprises forming an entirety of the magnetic inductor in the recess.

12. The method of claim 4 , further comprising overmolding the one of the plurality of uncore dies and the substrate with a molding compound or encapsulant.

13. The method of claim 4 , wherein forming the capacitor in or on the silicon wafer comprises forming a high density MIM capacitor embedded in the silicon wafer.

14. The method of claim 13 , wherein forming the high density MIM capacitor comprises forming a series of parallel channels or grooves in the silicon wafer, forming a first conductor layer in the series of parallel channels or grooves, forming a dielectric layer on the first conductor layer, and forming a second conductor layer on the dielectric layer.

15. The method of claim 14 , wherein forming the dielectric layer comprises forming a dielectric selected from the group consisting of Al 2 O 3 and HfO 2 .

16. The method of claim 14 , wherein the first conductor layer and the second conductor layer are a same material.

17. The method of claim 14 , wherein the first conductor layer and the second conductor layer are a different material.

18. The method of claim 6 , wherein forming the inductor in or on the silicon wafer comprises forming a recess in the silicon wafer, and forming a magnetic inductor in the recess, and wherein forming the capacitor in or on the silicon wafer comprises forming a high density MIM capacitor embedded in the silicon wafer.

Assignees

• Intel Corp

Inventors

• Sharan Sujit
• Mahajan Ravindranath
• Rusu Stefan
• Gardner Donald S

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title