Memory circuit capable of implementing calculation operations

Patent metadata

Field	Value
Publication number	US-11031076-B2
Application number	US-201916684987-A
Country	US
Kind code	B2
Filing date	Nov 15, 2019
Priority date	Nov 16, 2018
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns, the cells of a same column sharing a same read bit line and a same write bit line; an internal control circuit capable of implementing a calculation operation including the simultaneous activation in read mode of at least two rows of the array; and a shuffle circuit including a data input register, a configuration register, and an output port, the shuffle circuit being capable of delivering on its output port the data stored in its input register shuffled according to a shuffle operation defined according to the state of its configuration register.

First claim

What is claimed is:

1. A memory circuit comprising:
a plurality of elementary storage cells arranged in an array of rows and of columns, the cells of a same column sharing a same read bit line and a same write bit line;
an internal control circuit implementing a calculation operation comprising the simultaneous activation in read mode of at least two rows of the array; and
a shuffle circuit comprising a data input register, a configuration register, and an output port, the shuffle circuit delivering on its output port the data stored in its input register shuffled according to a shuffle operation defined according to a state of its configuration register,
wherein the shuffle circuit is a configurable routing circuit with a parallel architecture, such that the time of implementation of a shuffle operation is substantially constant whatever the respective contents of the input register and of the configuration register of the shuffle circuit are.

2. The memory circuit of claim 1 , wherein the control circuit implements a shuffle operation comprising a step of reading configuration data stored inside of the memory circuit and of copying the data into the configuration register of the shuffle circuit.

3. The memory circuit of claim 2 , wherein the shuffle operation comprises:
activating in read mode at least a first row of the array;
copying data read from the read bit lines of the array into the data input register of the shuffle circuit;
copying data supplied on the output port of the shuffle circuit onto the write bit lines of the array; and
activating in write mode at least one row of the array.

4. The memory circuit of claim 2 , wherein the shuffle operation comprises:
activating in read mode at least a second row of the array; and
copying data read from the read bit lines of the array into the configuration register of the shuffle circuit.

5. The memory circuit of claim 2 , comprising, in addition to the array of elementary storage cells, an additional memory intended to store data of configuration of the shuffle circuit.

6. The memory circuit of claim 5 , wherein the shuffle operation further comprises copying the data read from the additional memory into the configuration register of the shuffle circuit.

7. The memory circuit of claim 5 , wherein the additional memory is a non-volatile memory.

8. The memory circuit of claim 1 , wherein the shuffle circuit comprises a plurality of elementary shuffle cells, each comprising two data inputs e 1 and e 2 , two data outputs s 1 and s 2 , and one configuration input c.

9. The memory circuit of claim 8 , wherein the shuffle circuit comprises (K/2)*(2*log 2 (K)−1) elementary shuffle cells arranged in a Benes network, where K is an integer designating the dimension of the input register and of the output port of the shuffle circuit.

10. The memory circuit of claim 8 , wherein the shuffle circuit comprises 16 elementary shuffle cells arranged in 5 rows, the rows of rank 1=1 to 1=3 each comprising 4 elementary cells and the rows of rank 1=4 to 1=5 each comprising 2 elementary cells, the input register and the output port of the shuffle circuit being of dimension 8 , and 1 being an integer in the range from 1 to 5.

11. The memory circuit of claim 1 , further comprising an input-output circuit configurable to couple the read bit lines of the array to the input register of the shuffle circuit and/or to couple the write bit lines of the array to the output port of the shuffle circuit.

12. The memory circuit of claim 11 , further comprising a calculation circuit capable of implementing logic or arithmetic operations having data stored in the array of elementary storage cells of the memory circuit as operands.

13. The memory circuit of claim 12 , wherein the input-output circuit is further configurable to couple the read bit lines of the array to an input register of the calculation circuit and/or to couple the write bit lines of the array to an output port of the calculation circuit.

Assignees

• Commissariat Energie Atomique

Inventors

• Charles Henri-Pierre
• Kooli Maha
• Noel Jean-Philippe

Classifications

• G11C11/412

  using field-effect transistors only · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C11/417

  for memory cells of the field-effect type · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title