Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-11031065-B2
Application number	US-202017024259-A
Country	US
Kind code	B2
Filing date	Sep 17, 2020
Priority date	Jun 1, 2018
Publication date	Jun 8, 2021
Grant date	Jun 8, 2021

Abstract

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

First claim

What is claimed is:

1. A method of operating a semiconductor memory device including a memory cell array that includes a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of memory cells, the method comprising:
receiving a refresh request from a memory controller;
generating a scrubbing address for performing a scrubbing operation on at least one sub-page in a first memory cell row of the memory cell array based on the refresh request;
reading first data corresponding to a first codeword from the at least one sub-page and correcting at least one error bit in the first codeword; and
writing back the corrected first codeword in a memory location in which the first data is stored,
wherein the correcting and writing-back operations are performed by the semiconductor memory device by itself during a period of time by receiving the refresh request.

2. The method of claim 1 , wherein the refresh request is a self-refresh command.

3. The method of claim 2 , wherein the correcting and writing-back operations are performed instead of a refresh operation to be performed in response to the self-refresh command.

4. The method of claim 1 , wherein detecting the at least one error bit and correcting the at least one error bit are performed by an error correction code (ECC) engine in the semiconductor memory device.

5. The method of claim 1 , wherein the scrubbing address is different from a refresh row address generated by receiving the refresh request.

6. The method of claim 1 , wherein the scrubbing address includes a scrubbing row address designating the first memory cell row and a scrubbing column address designating the at least one sub-page.

7. The method of claim 1 , wherein the scrubbing operation is sequentially performed on all sub-pages in the first memory cell row.

8. The method of claim 1 , wherein the semiconductor memory device is a DRAM device.

9. A method of operating a semiconductor memory device including a memory cell array that includes a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of memory cells, the method comprising:
receiving a refresh request from a memory controller;
performing a read operation to read first data corresponding to a first codeword from at least one sub-page in a first memory cell row of the memory cell rows, and a correction operation to correct at least one error bit in the first codeword based on the refresh request; and
performing a write-back operation to write back the corrected first codeword in a memory location in which the first data is located,
wherein the correction and write-back operations are performed by the semiconductor memory device itself without being interrupted from the memory controller during a period of time by receiving the refresh request.

10. The method of claim 9 , wherein the refresh request is a self-refresh command.

11. The method of claim 10 , wherein the correction and the write-back operations are performed instead of a refresh operation to be performed in response to the self-refresh command.

12. The method of claim 9 , wherein detecting the at least one error bit and correcting the at least one error bit are performed by an error correction code (ECC) engine in the semiconductor memory device.

13. A memory system comprising:
a semiconductor memory device; and
a memory controller configured to issue a refresh request to the semiconductor memory device,
wherein the semiconductor memory device comprises:
a memory cell array that includes a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of memory cells;
a scrubbing address generator configured to generate a scrubbing address for performing a scrubbing operation on at least one sub-page in a first memory cell row among the plurality of memory cell rows; and
an error correction code (ECC) engine configured to read first data corresponding to a first codeword from the at least one sub-page, configured to correct at least one error bit in the first codeword and configured to write back the corrected first codeword in a memory location in which the first data is stored, in response to the scrubbing address.

14. The memory system of claim 13 , wherein the refresh request is a self-refresh command.

15. The memory system of claim 13 , wherein the scrubbing address includes a scrubbing row address designating the first memory cell row and a scrubbing column address designating the at least one sub-page.

16. The memory system of claim 13 , wherein the ECC engine is configured to sequentially perform the scrubbing operation on all sub-pages in the first memory cell row.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cha Sang-Uhn
• Kim Hyun-Gi
• Sin Hoon
• Ryu Ye-Sin
• Jun In-Woo

Classifications

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G11C2029/0409

  Online test · CPC title

• G11C29/4401

  for self repair · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title