Capacitively coupled continuous-time delta-sigma modulator and operation method thereof

Patent metadata

Field	Value
Publication number	US-11025269-B2
Application number	US-202016871082-A
Country	US
Kind code	B2
Filing date	May 11, 2020
Priority date	May 13, 2019
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

According to an exemplary embodiment, a capacitively coupled continuous-time delta-sigma modulator includes an instrumentation amplifier amplifying an input voltage to an output voltage of a predetermined magnitude, a delta-sigma modulator outputting a bit signal quantized depending on a sampling frequency based on the output voltage and to convert the bit signal into a digital-to-analog conversion voltage, and a ripple reduction loop unit generating a demodulation voltage, in which a ripple is removed from the output voltage, depending on an RRL operating frequency to feed the demodulation voltage back to the instrumentation amplifier. The RRL operating frequency is equal to the sampling frequency.

First claim

What is claimed is:

1. A capacitively coupled continuous-time delta-sigma modulator comprising:
an instrumentation amplifier configured to amplify an input voltage to generate an output voltage of a predetermined magnitude;
a delta-sigma modulator configured to:
output a bit signal quantized depending on a sampling frequency based on the output voltage; and
convert the bit signal into a digital-to-analog conversion voltage which is fed back to the instrumentation amplifier; and

a ripple reduction loop (RRL) unit configured to:
generate a demodulation voltage based on the output voltage, in which a ripple is removed from the output voltage, depending on an RRL operating frequency; and
feed the demodulation voltage back to the instrumentation amplifier,

wherein the RRL operating frequency is equal to the sampling frequency.

2. The capacitively coupled continuous-time delta-sigma modulator of claim 1 , wherein the instrumentation amplifier includes:
a first modulator configured to modulate the input voltage depending on a modulation frequency equal to the sampling frequency;
a second modulator configured to modulate at least one of an output of the first modulator and the demodulation voltage depending on the modulation frequency; and
a third modulator configured to modulate the output voltage depending on the modulation frequency.

3. The capacitively coupled continuous-time delta-sigma modulator of claim 2 , wherein the ripple reduction loop unit feeds the demodulation voltage back to the second modulator.

4. The capacitively coupled continuous-time delta-sigma modulator of claim 2 , wherein the instrumentation amplifier further includes:
a first amplifier, of which an input terminal is electrically connected to a first capacitor coupled to the first modulator; and
a second amplifier, of which an input terminal is connected to the second modulator and of which an output terminal is connected to a second capacitor,
wherein the input terminal of the second amplifier and the output terminal of the second amplifier are electrically connected through the second capacitor, and
wherein the output terminal of the second amplifier is electrically connected to the input terminal of the first amplifier through a third capacitor coupled to the third modulator.

5. The capacitively coupled continuous-time delta-sigma modulator of claim 4 , wherein the delta-sigma modulator includes:
a loop filter connected to the output terminal of the second amplifier and configured to perform low pass filtering on the output voltage depending on a preset loop transfer function;
a quantizer configured to quantize the low-pass-filtered output voltage as the bit signal; and
a digital-to-analog converter configured to convert the bit signal into the digital-to-analog conversion voltage to feed the digital-to-analog conversion voltage back to the input terminal of the first amplifier.

6. The capacitively coupled continuous-time delta-sigma modulator of claim 5 , wherein the preset loop transfer function includes a gain value corresponding to NULL for each sampling frequency.

7. The capacitively coupled continuous-time delta-sigma modulator of claim 1 , wherein the ripple reduction loop unit includes:
a loop sensing capacitor configured to sense the output voltage;
a ripple elimination demodulator configured to demodulate a charging voltage, which is charged through the loop sensing capacitor, as a first demodulation voltage depending on the RRL operating frequency;
a ripple elimination inverting amplifier configured to invert and amplify the first demodulation voltage;
a loop feedback capacitor configured to feed an output terminal of the ripple elimination inverting amplifier back to an inverting input terminal of the ripple elimination inverting amplifier; and
a ripple elimination non-inverting amplifier configured to non-invert and amplify the inverted and amplified first demodulation voltage as the demodulation voltage depending on a transconductance,
wherein the inverted and amplified first demodulation voltage is non-inverted and amplified as the demodulation voltage depending on the transconductance of the ripple elimination non-inverting amplifier.

8. The capacitively coupled continuous-time delta-sigma modulator of claim 7 , wherein a capacitance of the loop sensing capacitor is preset to a value reduced at a first decrease ratio based on a preset target increase ratio of a signal-to-noise ratio.

9. The capacitively coupled continuous-time delta-sigma modulator of claim 8 , wherein the transconductance is preset to a value reduced at a second decrease ratio based on the preset target increase ratio of the signal-to-noise ratio, and
wherein the second decrease ratio is less than the first decrease ratio.

10. An operation method of a capacitively coupled continuous-time delta-sigma modulator, the method comprising:
amplifying, by an instrumentation amplifier, an input voltage to generate an output voltage of a predetermined magnitude;
outputting, by a delta-sigma modulator, a bit signal quantized depending on a sampling frequency based on the output voltage;
converting, by the delta-sigma modulator, the bit signal into a digital-to-analog conversion voltage which is fed back to the instrumental amplifier;
generating, by a ripple reduction loop (RRL) unit, a demodulation voltage based on the output voltage, in which a ripple is removed from the output voltage, depending on an RRL operating frequency equal to the sampling frequency; and
feeding, by the RRL unit, the demodulation voltage generated based on the output voltage back to the instrumentation amplifier.

11. A capacitively coupled continuous-time delta-sigma modulator comprising:
an instrumentation amplifier configured to amplify an input voltage to generate an output voltage of a predetermined magnitude;
a delta-sigma modulator configured to output a bit signal quantized depending on a sampling frequency based on the output voltage, and convert the bit signal into a digital-to-analog conversion voltage; and
a ripple reduction loop (RRL) unit configured to generate a demodulation voltage, in which a ripple is removed from the output voltage, depending on an RRL operating frequency equal to the sampling frequency, and feed the demodulation voltage back to the instrumentation amplifier,
wherein the instrumentation amplifier comprises:
a first modulator configured to modulate the input voltage depending on a modulation frequency equal to the sampling frequency;
a second modulator configured to modulate at least one of an output of the first modulator and the demodulation voltage depending on the modulation frequency; and
a third modulator configured to modulate the output voltage depending on the modulation frequency.

12. The capacitively coupled continuous-time delta-sigma modulator of claim 11 , wherein the RRL unit feeds the demodulation voltage back to the second modulator.

13. The capacitively coupled continuous-time delta-sigma modulator of claim 11 , wherein the RRL unit comprises:
a loop sensing capacitor configured to sense the output voltage;
a ripple elimination demodulator configured to demodulate a charging voltage which is charged through the loop sensing capacitor as a first demodulation voltage depending on the RRL operating frequency;
a ripple elimination inverting amplifier configured to invert and amplify the first demodulation voltage;
a loop feedback capacitor configured to feed an output terminal of the ripple elimination inverting amplifier back to an inverting input terminal of the ripple elimination inverting amplifier; and
a ripple elimination non

Assignees

• Univ Korea Res & Bus Found

Inventors

• Kim Chulwoo
• Lim Chae Kang
• Choi Yo Han

Classifications

• H03M3/344

  by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing · CPC title

• H03M3/34

  by chopping · CPC title

• H03M3/422

  having one quantiser only · CPC title

• H03F3/04

  with semiconductor devices only · CPC title

• H03F2200/261

  Amplifier which being suitable for instrumentation applications · CPC title