Nonvolatile memory apparatus for performing a read operation and a method of operating the same

Patent metadata

Field	Value
Publication number	US-11024377-B2
Application number	US-201916677146-A
Country	US
Kind code	B2
Filing date	Nov 7, 2019
Priority date	Feb 27, 2019
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.

First claim

What is claimed is:

1. A nonvolatile memory apparatus comprising:
a memory cell coupled between a bit line electrode and a word line electrode;
a read voltage circuit configured to apply a first high-bias voltage to the bit line electrode based on a first read control signal and apply a second high-bias voltage to the bit line electrode based on a second read control signal;
a read current circuit configured to allow a first current to flow through the word line electrode during a read operation and allow a second current to flow through the word line electrode based on a repair signal; and
a snap-back detection circuit configured to generate a detection signal by detecting a snap-back of the memory cell, generate a read termination signal based on the first read control signal and the detection signal, and generate the repair signal based on the detection signal, the read termination signal, and the second read control signal;
wherein, the first read control signal controls a first read operation on the memory cell and wherein the second read control signal controls a second read operation on the memory cell.

2. The nonvolatile memory apparatus of claim 1 , wherein the second high-bias voltage has a higher voltage level than the first high-bias voltage.

3. The nonvolatile memory apparatus of claim 1 , wherein the read voltage circuit comprises:
a first voltage supply circuit configured to receive the first high-bias voltage and apply the first high-bias voltage to the bit line electrode based on the first read control signal; and
a second voltage supply circuit configured to receive the second high-bias voltage and apply the second high-bias voltage to the bit line electrode based on the second read control signal.

4. The nonvolatile memory apparatus of claim 1 , wherein the second current is greater than the first current.

5. The nonvolatile memory apparatus of claim 1 , wherein the second current is a repair current for forming the memory cell in a low-resistance state.

6. The nonvolatile memory apparatus of claim 1 , wherein the read current circuit comprises:
a first current supply circuit configured to allow the first current to flow through the word line electrode based on a read signal; and
a second current supply circuit configured to allow the second current to flow through the word line electrode based on the repair signal.

7. The nonvolatile memory apparatus of claim 6 ,
wherein the first current supply circuit is further configured to receive a first low-bias voltage and provide the word line electrode with the first low-bias voltage, and
wherein the second current supply circuit is further configured to receive a second low-bias voltage and provide the word line electrode with the second low-bias voltage.

8. The nonvolatile memory apparatus of claim 7 , wherein the second low-bias voltage has a lower voltage level than the first low-bias voltage.

9. The nonvolatile memory apparatus of claim 8 , wherein:
a voltage level difference between the first high-bias voltage and the first low-bias voltage corresponds to a voltage level of a first read voltage;
a voltage level difference between the second high-bias voltage and the first low-bias voltage corresponds to a voltage level of a second read voltage; and
the second read voltage has a higher voltage level than the first read voltage.

10. The nonvolatile memory apparatus of claim 9 , wherein:
the first read voltage has a voltage level higher than a set distribution minimum voltage and lower than a set distribution maximum voltage; and
the second read voltage has a voltage level higher than the set distribution maximum voltage and lower than a reset distribution minimum voltage.

11. The nonvolatile memory apparatus of claim 1 , wherein the snap-back detection circuit is coupled to the word line electrode and configured to generate the detection signal by detecting a voltage level of the word line electrode.

12. The nonvolatile memory apparatus of claim 1 , wherein the snap-back detection circuit comprises:
a comparator configured to generate the detection signal by comparing a voltage level of the word line electrode with a voltage level of a reference voltage;
a read termination signal generation circuit configured to generate a read termination signal based on the detection signal and the first read control signal; and
a repair signal generation circuit configured to generate the repair signal based on the detection signal, the read termination signal, and the second read control signal.

13. The nonvolatile memory apparatus of claim 12 ,
wherein the read termination signal generation circuit is configured to enable the read termination signal when the detection signal becomes enabled while the first read control signal is enabled, and
wherein the read termination signal generation circuit is configured to disable the read termination signal when the first read control signal is disabled.

14. The nonvolatile memory apparatus of claim 1 , further comprising a read pulse generation circuit configured to generate the first read control signal and the second read control signal based on a read signal and a read termination signal.

15. The nonvolatile memory apparatus of claim 1 , wherein:
the first read control signal is enabled for a first amount of time;
the second read control signal is enabled for a second amount of time; and
the second amount of time is longer than the first amount of time.

Assignees

• Sk Hynix Inc

Inventors

• Kang Seok Joon
• Park Moo Hui
• Cheon Jun Ho

Classifications

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C13/0038

  Power supply circuits · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title