Cache diagnostic techniques

Patent metadata

Field	Value
Publication number	US-11023342-B2
Application number	US-201916264118-A
Country	US
Kind code	B2
Filing date	Jan 31, 2019
Priority date	Nov 30, 2018
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

Techniques are disclosed relating to cache debug using control registers based on debug commands. In some embodiments, an apparatus includes a processor core, debug circuitry, and control circuitry. In some embodiments, the debug circuitry is configured to receive external debug inputs and send abstract commands to the processor core based on the external debug inputs. In some embodiments, the control circuitry is configured to, in response to an abstract command to read data from the cache: write cache address information to a first control register, assert a trigger signal to cause a read of the data from the cache to a second control register, based on the cache address information in the first control register, and send data from the second control register to the debug circuitry. In various embodiments, this may facilitate hardware cache debug using debug circuitry that also controls software debugging.

First claim

What is claimed is:

1. An apparatus, comprising:
a processor core that includes a cache;
debug circuitry configured to receive external debug inputs and send abstract commands to the processor core based on the external debug inputs; and
control circuitry in the processor core configured to, in response to an abstract command to read data from the cache:
write cache address information to a first control register;
assert a trigger signal to cause a read of the data from the cache to a second control register, based on the cache address information in the first control register,

wherein the data includes tag data for one or more cache lines of the cache and status data for one or more cache lines of the cache; and
send the data from the second control register to the debug circuitry.

2. The apparatus of claim 1 , wherein the trigger signal is a register read.

3. The apparatus of claim 1 , wherein the data includes cached instruction data and error protection information for the cached instruction data.

4. The apparatus of claim 1 , wherein the cache address information specifies an array, a way, and an index.

5. The apparatus of claim 1 , wherein the control circuitry is further configured to, in response to an abstract command from the debug circuitry to write data to the cache:
write data to a control register; and
assert a trigger signal to cause a write of the data from the control register to the cache, based on the cache address information.

6. The apparatus of claim 5 , wherein the control circuitry is further configured to write error protection information to the cache for the written data.

7. The apparatus of claim 1 , wherein the control registers are accessible only in a debug mode of the processor core.

8. A method, comprising:
receiving, by debug circuitry, external debug inputs and sending abstract commands to a processor core based on the external debug inputs; and
in response to an abstract command to read data from a cache in the processor core:
writing, by control circuitry, cache address information to a first control register;
asserting, by the control circuitry, a trigger signal to cause a read of the data from the cache to a second control register, based on the cache address information in the first control register, wherein the data includes tag data for one or more cache lines of the cache and status data for one or more cache lines of the cache; and
sending the data from the second control register to the debug circuitry.

9. The method of claim 8 , wherein the trigger signal is a register read.

10. The method of claim 8 , wherein the data includes cached instruction data and error protection information for the cached instruction data.

11. The method of claim 8 , further comprising, in response to an abstract command from the debug circuitry to write data to the cache:
writing, by the control circuitry, data to a control register; and
asserting, by the control circuitry, a trigger signal to cause a write of the data from the control register to the cache, based on the cache address information.

12. A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, including:
a processor core that includes a cache;
debug circuitry configured to receive external debug inputs and send abstract commands to the processor core based on the external debug inputs; and
control circuitry in the processor core configured to, in response to an abstract command to read data from the cache:
write cache address information to a first control register;
assert a trigger signal to cause a read of the data from the cache to a second control register, based on the cache address information in the first control register, wherein the data includes tag data for one or more cache lines of the cache and status data for one or more cache lines of the cache; and
send the data from the second control register to the debug circuitry.

13. The non-transitory computer readable storage medium of claim 12 , wherein the trigger signal is a register read.

14. The non-transitory computer readable storage medium of claim 12 , wherein the data includes cached instruction data and error protection information for the cached instruction data.

15. The non-transitory computer readable storage medium of claim 12 , wherein the cache address information specifies an array, a way, and an index.

16. The non-transitory computer readable storage medium of claim 12 , wherein the control circuitry is further configured to, in response to an abstract command from the debug circuitry to write data to the cache:
write data to a control register; and
assert a trigger signal to cause a write of the data from the control register to the cache, based on the cache address information.

17. The non-transitory computer readable storage medium of claim 16 , wherein the control circuitry is further configured to write error protection information to the cache for the written data.

Assignees

• Western Digital Tech Inc

Inventors

• Barreh Jama I
• Golla Robert T
• Wicki Thomas M
• Smittle Matthew B

Classifications

• G06F11/2736

  using a dedicated service processor for test · CPC title

• G06F11/2236 Primary

  to test CPU or processors · CPC title

• G06F11/263 Primary

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title

• G06F9/30101

  Special purpose registers · CPC title