Reprogramming a port controller via its own external port

Patent metadata

Field	Value
Publication number	US-9606175-B2
Application number	US-201414583218-A
Country	US
Kind code	B2
Filing date	Dec 26, 2014
Priority date	Dec 26, 2014
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Systems and methods may provide for a debug tool including a debug port and a controller including logic to send, via the debug port, a debug mode request to an external port of a target device. Additionally, the target device may include a connector having the external port and a port controller coupled to the external port, wherein the port controller includes logic to detect the debug mode request via the external port, activate a program path between the external port and the port controller in response to the debug mode request, and process one or more commands received via the program path. In one example, the target device further includes a multiplexer coupled to the external port and the port controller, wherein the logic is to send a routing signal to the multiplexer to activate the program path.

First claim

We claim:

1. A device comprising:
a connector including an external port;
a port controller including logic to:
detect a debug mode request via the external port,
activate a program path between the external port and the port controller in response to the debug mode request, and
process one or more commands received via the program path; and

a multiplexer coupled to the external port and the port controller, wherein the logic is to send a routing signal to the multiplexer to activate the program path.

2. The device of claim 1 , further including a host processor, wherein the program path bypasses the host processor.

3. The device of claim 1 , wherein the one or more commands are to be processed while the device lacks internal power.

4. A device comprising:
a connector including an external port;
a port controller including logic to:
detect a debug mode request via the external port,
activate a program path between the external port and the port controller in response to the debug mode request, and

process one or more commands received via the program path; and
non-volatile memory associated with the port controller, wherein the logic is to:
receive code via the program path, wherein the code is to include one or more of a runtime firmware image or a debug bootloader; and
store the code to the non-volatile memory.

5. The device of claim 1 , wherein the one or more commands are to include one or more of a reprogram command, a reset command or a diagnostic command.

6. A debug tool comprising:
a debug port; and
a controller including logic to send, via the debug port, a debug mode request to an external port of a target device wherein, to send the debug mode request, the logic is to:
assert an enable signal to the debug port;
apply a predetermined resistance to the debug port; and
apply power to the debug port.

7. A debug tool comprising:
a debug port; and
a controller including logic to send, via the debug port, a debug mode request to an external port of a target device;
a first switch coupled to a first configuration channel contact of the debug port;
a first resistor coupled to the first switch;
a second switch coupled to a second configuration channel contact of the debug port; and
a second resistor coupled to the second switch, wherein the logic is to activate the first switch and the second switch to apply the predetermined resistance to the debug port.

8. The debug tool of claim 6 , further including:
a set of power transistors coupled to a voltage bus contact of the debug port; and
a power port coupled to the set of power transistors, wherein the logic is to activate the set of power transistors to apply power to the debug port.

9. The debug tool of claim 6 , wherein the logic is to send, via the debug port, one or more commands to the external port of the target device, wherein the one or more commands include one or more of a reprogram command, a reset command or a diagnostic command.

10. A debug tool comprising:
a debug port; and
a controller including logic to send, via the debug port, a debug mode request to an external port of a target device, wherein the logic is to send, via the debug port, code to the external port of the target device, wherein the code includes one of a runtime firmware image or a debug bootloader.

11. A method of operating a port controller, comprising:
detecting, at the port controller, a debug mode request via an external port of a connector;
activating a program path between the external port and the port controller in response to the debug mode request, wherein activating the program path includes sending a routing signal to a multiplexer coupled to the external port; and
processing, at the port controller, one or more commands received via the program path.

12. The method of claim 11 , wherein the program path bypasses a host processor of a target device containing the port controller.

13. The method of claim 11 , wherein the one or more commands are processed while a target device containing the port controller lacks internal power.

14. A method of operating a port controller, comprising:
detecting, at the port controller, a debug mode request via an external port of a connector;
activating a program path between the external port and the port controller in response to the debug mode request; and
processing, at the port controller, one or more commands received via the program path;
receiving code via the program path, wherein the code includes one or more of a runtime firmware image or a debug bootloader; and
storing the code to non-volatile memory associated with the port controller.

15. The method of claim 11 , wherein the one or more commands include one or more of a reprogram command, a reset command or a diagnostic command.

16. At least one non-transitory computer readable storage medium comprising a set of instructions which, when executed by a port controller, cause the port controller to:
detect a debug mode request via an external port of a connector;
activate a program path between the external port and the port controller in response to the debug mode request;
process one or more commands received via the program path; and
send a routing signal to a multiplexer coupled to the external port to activate the program path.

17. The at least one non-transitory computer readable storage medium of claim 16 , wherein the program path is to bypass a host processor of a target device containing the port controller.

18. The at least one non-transitory computer readable storage medium of claim 16 , wherein the one or more commands are to be processed while a target device containing the port controller lacks internal power.

19. At least one non-transitory computer readable storage medium comprising a set of instructions which, when executed by a port controller, cause the port controller to:
detect a debug mode request via an external port of a connector;
activate a program path between the external port and the port controller in response to the debug mode request; and
process one or more commands received via the program path;
receive code via the program path, wherein the code is to include one or more of a runtime firmware image or a debug bootloader; and
store the code to non-volatile memory associated with the port controller.

20. The at least one non-transitory computer readable storage medium of claim 16 , wherein the one or more commands are to include one or more of a reprogram command, a reset command or a diagnostic command.

Assignees

• Intel Corp

Inventors

• Trethewey James R
• Adamson Peter S
• Valavi John J
• Narayanan Anantha
• Palanisamy Kandasubramaniam K
• Saad Ihab W

Classifications

• G06F11/2236

  to test CPU or processors · CPC title

• G06F11/26

  Functional testing · CPC title

• G06F11/3656

  using a specific debug interface · CPC title

• G01R31/31705 Primary

  Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544) · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title