Solid-state imaging device and electronic apparatus

Patent metadata

Field	Value
Publication number	US-11019296-B2
Application number	US-201916516832-A
Country	US
Kind code	B2
Filing date	Jul 19, 2019
Priority date	Jan 28, 2010
Publication date	May 25, 2021
Grant date	May 25, 2021

Abstract

A solid-state imaging device includes a pixel region in which shared pixels which share pixel transistors in a plurality of photoelectric conversion portions are two-dimensionally arranged. The shared pixel transistors are divisionally arranged in a column direction of the shared pixels, the pixel transistors shared between neighboring shared pixels are arranged so as to be horizontally reversed or/and vertically crossed, and connection wirings connected to a floating diffusion portion, a source of a reset transistor and a gate of an amplification transistor in the shared pixels are arranged along the column direction.

First claim

What is claimed is:

1. A light detecting device comprising:
a first unit including:
a first photoelectric conversion region disposed in a first row,
a second photoelectric conversion region disposed in a second row,
a first floating diffusion coupled to the first photoelectric conversion region and the second photoelectric conversion region,
a first reset transistor coupled to the first floating diffusion, and
a first amplification transistor coupled to the first floating diffusion;

a second unit disposed adjacent to the first unit in a row direction, the second unit including:
a third photoelectric conversion region disposed in the first row,
a fourth photoelectric conversion region disposed in the second row,
a second floating diffusion coupled to the third photoelectric conversion region and the fourth photoelectric conversion region,
a second reset transistor coupled to the second floating diffusion, and
a second amplification transistor coupled to the second floating diffusion,

wherein a first distance between a gate terminal of the first amplification transistor and a first column line disposed between the first photoelectric conversion region and the third photoelectric conversion region is the same as a second distance between a gate terminal of the second amplification transistor and the first column line.

2. The light detecting device of claim 1 , wherein
the first row is different from the second row,
the first amplification transistor and the second reset transistor are disposed in a third row, the third row disposed between the first row and the second row, and
the second amplification transistor arranged in same row as the first reset transistor.

3. The light detecting device of claim 1 , wherein
the first photoelectric conversion region, the second photoelectric conversion region, and the gate terminal of the first amplification transistor are disposed in a first column, and
the third photoelectric conversion region, the fourth photoelectric conversion region, and the gate terminal of the second amplification transistor are disposed in a second column.

4. The light detecting device of claim 1 , wherein
the first unit further includes a first transfer transistor and a second transfer transistor coupled to the first photoelectric conversion region, and
the second unit further includes a third transfer transistor and a fourth transfer transistor coupled to the fourth photoelectric conversion region.

5. The light detecting device of claim 4 , wherein
the first unit further includes a first wiring coupled to the first amplification transistor, and
the first transfer transistor and the second transfer transistor are coupled to the first wiring.

6. The light detecting device of claim 5 , wherein
the second unit further includes a second wiring coupled to the second amplification transistor, and
the third transfer transistor and the fourth transfer transistor are coupled to the second wiring.

7. The light detecting device of claim 4 , wherein
from a plan view perspective, a gate terminal of the first transfer transistor has a hexagonal shape including a first edge and a second edge,
the first edge is the longest edge in the hexagonal shape and
the second edge is located opposite to the first edge, and is located farther from the first floating diffusion than the first edge.

8. The light detecting device of claim 1 , further comprising:
a first line extending in a column direction which is perpendicular to the row a row direction, the first line being disposed between the first floating diffusion and the second floating diffusion,
wherein a first distance between a gate terminal of the first amplification transistor and the first line is the same as a second distance between a gate terminal of the second amplification transistor and the first line.

9. The light detecting device of claim 8 , wherein
a third distance between a gate terminal of the first selection transistor and the first line is the same as a fourth distance between a gate terminal of the second selection transistor and the first line.

10. The light detecting device of claim 1 , further comprising
a first wiring coupled to a source of the first reset transistor, to the first floating diffusion, and to a gate terminal of the first amplification transistor; and
a second wiring coupled to a source of the second reset transistor, to the second floating diffusion, and to a gate terminal of the second amplification transistor,
wherein a length of the first wiring is the same as a length of the second wiring.

11. A light detecting device comprising:
a first unit including:
a first floating diffusion,
a first transfer transistor coupled to the first floating diffusion,
a first reset transistor coupled to the first floating diffusion,
a first amplification transistor coupled to the first floating diffusion, and
a first selection transistor coupled to the first floating diffusion; and

a second unit disposed adjacent to the first unit in a row direction, the second unit including:
a second floating diffusion,
a second transfer transistor coupled to the second floating diffusion,
a second reset transistor coupled to the second floating diffusion,
a second amplification transistor coupled to the second floating diffusion, and
a second selection transistor coupled to the first floating diffusion,

wherein a first distance between a gate terminal of the first amplification transistor and a first column line disposed between the first floating diffusion and the second floating diffusion is the same as a second distance between a gate of the second amplification transistor and the first column line.

12. The light detecting device of claim 11 , wherein
a gate terminal of the first reset transistor and a gate terminal of the second reset transistor are disposed in a first row,
a gate terminal of the first transfer transistor and a gate terminal of the third transfer transistor are disposed in a second row, and
the first floating diffusion and the second floating diffusion are disposed in a third row, the third row being disposed between the first row and the second row.

Assignees

• Sony Corp

Inventors

• Kido Hideo
• Yamamoto Atsuhiko
• Yamada Akihiro

Classifications

• H04N25/767 Primary

  Horizontal readout lines, multiplexers or registers · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/7795

  Circuitry for generating timing or clock signals · CPC title

• H10F39/802 Primary

  Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title