Fault interrupt module

US11018490B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11018490-B2
Application numberUS-201916246710-A
CountryUS
Kind codeB2
Filing dateJan 14, 2019
Priority dateFeb 7, 2018
Publication dateMay 25, 2021
Grant dateMay 25, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A fault interrupt module includes a detector circuit, a counter circuit, and a switch circuit. The detector circuit is configured to detect faults as a difference in current between an input power line and a neutral line. The counter circuit configured to increment a fault count each time a fault is detected by the detector circuit, and the switch circuit is configured to terminate power to a load upon the fault count reaching a threshold count within a threshold time period.

First claim

Opening claim text (preview).

The invention claimed is: 1. A fault interrupt module comprising: a detector circuit configured to detect faults as a difference in current between an input power line and a neutral line; a counter circuit configured to increment a fault count each time a fault is detected by the detector circuit; a switch circuit configured to terminate power to a load upon the fault count reaching a threshold count within a threshold time period; a first timer configured to output a first pulse for a first time period upon receipt of the detector pulse; and a second timer configured to output a second pulse for a second time period upon receipt of the detector pulse, wherein the threshold time period is the second time period. 2. The fault interrupt module of claim 1 , wherein the second time period is greater than the first time period. 3. The fault interrupt module of claim 1 , wherein the switch circuit is further configured to terminate the power to the load during the first pulse. 4. The fault interrupt module of claim 1 , wherein the counter circuit is configured to output a counter pulse upon the fault count reaching the threshold count within the second time period. 5. The fault interrupt module of claim 4 , further comprising a latch configured to latch the counter pulse to maintain the switch circuit in an OFF state. 6. The fault interrupt module of claim 1 , wherein the load is an aircraft heated floor panel. 7. A method of controlling input power to a load, the method comprising: detecting, by a detector circuit, faults on the input power; outputting, by a detector circuit, a detector pulse upon detection of each of the faults; incrementing, by a counter circuit, a fault count upon receipt of the detector pulse; terminating, by a switch circuit, the input power upon the fault count reaching a threshold count within a threshold time period; outputting, by a first timer circuit, a first pulse upon receipt of the detector pulse; and terminating, by the switch circuit, the input power during the first pulse. 8. The method of claim 7 , wherein detecting, by the detector circuit, the faults on the input power comprises detecting a difference in current between an input power line and a neutral line. 9. The method of claim 7 , further comprising: outputting, by a second timer circuit, a second pulse, greater than the first pulse, as the threshold time period upon receipt of the detector pulse. 10. The method of claim 9 , and wherein the method further comprises: outputting, by the counter circuit, a counter pulse if the fault count reaches the threshold count within the second pulse. 11. The method of claim 10 , further comprising: latching the counter pulse as a latched signal; and providing the latched signal to the switch circuit, wherein the switch circuit is configured to terminate the input power based on the latched signal. 12. The method of claim 7 , wherein the input power is alternating current (AC) power and the load is a heated floor panel for an aircraft. 13. A circuit configured to control input power to a load, the circuit comprising: an input coil configured to output a difference in current between an input line that carries the input power and a neutral return line; a detector circuit configured to output a detector pulse when the difference in current is greater than a threshold value; a counter circuit configured to increment a fault count each time the detector circuit outputs the detector pulse; a solid state relay circuit configured to terminate power to the load upon the fault count reaching a threshold count; a first timer configured to output a first pulse for a first time period upon receipt of the detector pulse; and a second timer configured to output a second pulse for a second time period upon receipt of the detector pulse. 14. The circuit of claim 13 , wherein the second time period is greater than the first time period. 15. The circuit of claim 13 , wherein the solid state relay circuit is further configured to terminate the power to the load during the first pulse. 16. The circuit of claim 13 , wherein the counter circuit is configured to output a counter pulse upon the fault count reaching the threshold count within the second time period. 17. The circuit of claim 16 , further comprising a latch configured to latch the counter pulse to maintain the solid state relay in an OFF state.

Assignees

Inventors

Classifications

  • and with permanent disconnection after a predetermined number of reconnection cycles · CPC title

  • using summation current transformers (H02H3/347 takes precedence) · CPC title

  • Energy efficient heating, ventilation or air conditioning [HVAC] · CPC title

  • concerning the detecting means (in general G01R or other subclasses of G01; reed switches H01H71/2445) · CPC title

  • Passenger or crew accommodation; Flight-deck installations not otherwise provided for · CPC title

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Frequently asked questions

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What does patent US11018490B2 cover?
A fault interrupt module includes a detector circuit, a counter circuit, and a switch circuit. The detector circuit is configured to detect faults as a difference in current between an input power line and a neutral line. The counter circuit configured to increment a fault count each time a fault is detected by the detector circuit, and the switch circuit is configured to terminate power to a l…
Who is the assignee on this patent?
Goodrich Corp
What technology area does this patent fall under?
Primary CPC classification F24D13/02. Mapped technology areas include Mechanical Engineering.
When was this patent published?
Publication date Tue May 25 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).