Semiconductor device with multi-branch gate contact structure

Patent metadata

Field	Value
Publication number	US-11018250-B2
Application number	US-201916404005-A
Country	US
Kind code	B2
Filing date	May 6, 2019
Priority date	May 6, 2019
Publication date	May 25, 2021
Grant date	May 25, 2021

Abstract

According to an embodiment of a semiconductor device, the semiconductor device includes: a first active cell area comprising a first plurality of parallel gate trenches; a second active cell area comprising a second plurality of parallel gate trenches; and a metallization layer above the first and the second active cell areas. The metallization layer includes: a first part contacting a semiconductor mesa region between the plurality of parallel gate trenches in the first and the second active cell areas; and a second part surrounding the first part. The second part of the metallization layer contacts the first plurality of gate trenches along a first direction and the second plurality of gate trenches along a second direction different from the first direction.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first group of gate trenches formed in a semiconductor substrate and extending lengthwise in parallel in a first direction, each gate trench of the first group comprising a gate electrode above and electrically isolated from a field electrode;
a second group of gate trenches formed in the semiconductor substrate and extending lengthwise in parallel in a second direction transverse to the first direction, each gate trench of the second group comprising a gate electrode above and electrically isolated from a field electrode; and
a first metallization layer overlying the semiconductor substrate and comprising a source contact structure and a gate contact structure electrically isolated from the source contact structure,
wherein the gate electrodes of the first group of gate trenches are electrically connected at a same end to a first branch of the gate contact structure which extends lengthwise in a direction orthogonal to the first direction,
wherein the gate electrodes of the second group of gate trenches are electrically connected at a same end by a second branch of the gate contact structure which extends lengthwise in a direction orthogonal to the second direction,
wherein the field electrodes of the first group of gate trenches are electrically connected to the source contact structure at an opposite end from which the gate electrodes of the first group are electrically connected to the first branch of the gate contact structure,
wherein the field electrodes of the second group of gate trenches are electrically connected to the source contact structure at an opposite end from which the gate electrodes of the second group are electrically connected to the second branch of the gate contact structure.

2. The semiconductor device of claim 1 , wherein the first metallization layer is separated from the semiconductor substrate by an insulating layer, wherein the gate electrodes of the first group of gate trenches are electrically connected to the first branch of the gate contact structure through first contact openings which extend through the insulating layer, wherein the gate electrodes of the second group of gate trenches are electrically connected to the second branch of the gate contact structure through second contact openings which extend through the insulating layer, wherein the field electrodes of the first group of gate trenches are electrically connected to the source contact structure through third contact openings which extend through the insulating layer, and wherein the field electrodes of the second group of gate trenches are electrically connected to the source contact structure through fourth contact openings which extend through the insulating layer.

3. The semiconductor device of claim 2 , wherein the first branch of the gate contact structure runs between the first group of gate trenches and the second group of gate trenches, wherein the first branch of the gate contact structure is covered by an additional insulating layer, and wherein a top metal layer in contact with the source contact structure of the first metallization layer is separated from the first branch of the gate contact structure by the additional insulating layer.

4. The semiconductor device of claim 1 , wherein the gate contact structure is uninterrupted and forms a closed loop, and wherein the first branch and the second branch of the gate contact structure are joined together.

5. The semiconductor device of claim 1 , wherein the first direction is orthogonal to the second direction.

6. The semiconductor device of claim 1 , wherein the first metallization layer comprises a gate pad connected to the gate contact structure, and wherein the first group of gate trenches is longer than the second group of trenches and laterally overlaps with the gate pad.

7. The semiconductor device of claim 1 , further comprising a sensor formed in the semiconductor substrate between the first group of trenches and the second group of trenches.

8. The semiconductor device of claim 1 , further comprising:
a third group of gate trenches formed in the semiconductor substrate and extending lengthwise in parallel in the second direction, each gate trench of the third group comprising a gate electrode above and electrically isolated from a field electrode,
wherein the first direction is orthogonal to the second direction,
wherein the third group of gate trenches is adjacent the second group of gate trenches,
wherein the third group of gate trenches is shorter than the second group of gate trenches, and
wherein the third group of gate trenches and the second group of gate trenches terminate facing the first group of gate trenches.

9. A semiconductor device, comprising:
a first quadrant of gate trenches formed in a semiconductor substrate and comprising four groups of stripe-shaped gate trenches extending lengthwise in directions which are transverse to one another;
a second quadrant of gate trenches formed in the semiconductor substrate adjacent the first quadrant of gate trenches and comprising four groups of stripe-shaped gate trenches extending lengthwise in directions which are transverse to one another; and
a first metallization layer overlying the semiconductor substrate and comprising a gate contact structure electrically connected to gate electrodes in the gate trenches of the first and the second quadrants, the gate contact structure having a branch which runs along each side of the first and the second quadrants of gate trenches, including a branch between the first and the second quadrants of gate trenches,
wherein the first metallization layer comprises a first source contact structure and a second source contact structure electrically isolated from the gate contact structure,
wherein the first source contact structure is positioned above the first quadrant of gate trenches and electrically connected to field electrodes in the gate trenches of the first quadrant of gate trenches,
wherein the second source contact structure is positioned above the second quadrant of gate trenches and electrically connected to field electrodes in the gate trenches of the second quadrant of gate trenches.

10. The semiconductor device of claim 9 , wherein the branch of the gate contact structure between the first and the second quadrants of gate trenches runs uninterrupted along the entire length of the first and the second quadrants of gate trenches.

11. The semiconductor device of claim 9 , wherein the branch of the gate contact structure between the first and the second quadrants of gate trenches is interrupted along the length of the first and the second quadrants of gate trenches.

12. The semiconductor device of claim 9 , wherein the branch of the gate contact structure between the first and the second quadrants of gate trenches runs uninterrupted between the first source contact structure and the second source contact structure.

13. The semiconductor device of claim 9 , wherein the first source contact structure and the second source contact structure are electrically connected to one another by a metal bridge which extends through a break in the branch of the gate contact structure between the first and the second quadrants of gate trenches.

14. The semiconductor device of claim 9 , wherein the branch of the gate contact structure between the first and the second quadrants of gate trenches is covered by an insulating layer, and wherein a top metal layer in contact with the first source contact structure and the second source contact structure of the first metallization layer is separated from the branch of the gat

Assignees

• Infineon Technologies Ag

Inventors

• Zundel Markus
• Mieslinger Stefan
• Ostermann Thomas
• Wood Andrew Christopher Graeme

Classifications

• H10D64/511

  for IGFETs · CPC title

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D64/252

  for vertical or pseudo-vertical devices · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title