Techniques to provide cache coherency based on cache type

Patent metadata

Field	Value
Publication number	US-11016894-B2
Application number	US-201715670171-A
Country	US
Kind code	B2
Filing date	Aug 7, 2017
Priority date	Aug 7, 2017
Publication date	May 25, 2021
Grant date	May 25, 2021

Abstract

Techniques and apparatus to manage cache coherency for different types of cache memory are described. In one embodiment, an apparatus may include at least one processor, at least one cache memory, and logic, at least a portion comprised in hardware, the logic to receive a memory operation request associated with the at least one cache memory, determine a cache status of the memory operation request, the cache status indicating one of a giant cache status or a small cache status, perform the memory operation request via a small cache coherence process responsive to the cache status being a small cache status, and perform the memory operation request via a giant cache coherence process responsive to the cache status being a small cache status. Other embodiments are described and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
at least one processor;
at least one cache memory;
at least one system memory to store a directory comprising cache status information to indicate whether the at least one cache memory is a giant cache or a small cache; and
logic, at least a portion comprised in hardware, the logic to:
receive a memory operation request associated with the at least one cache memory,
determine a cache status of the memory operation request, the cache status indicating one of a giant cache status or a small cache status,
perform the memory operation request via a small cache coherence process responsive to a determination that the cache status is a small cache status, and
perform the memory operation request via a giant cache coherence process responsive to the determination that the cache status is a giant cache status.

2. The apparatus of claim 1 , the at least one cache memory comprising at least one small cache and at least one giant cache.

3. The apparatus of claim 1 , the at least one cache memory comprising at least one giant cache having a memory size greater than 1 gigabyte (GB).

4. The apparatus of claim 1 , the at least one cache memory comprising at least one small cache having a memory size of less than or equal to 10 megabytes (MB).

5. The apparatus of claim 1 , further comprising a logic device, the at least one cache memory operably coupled to the logic device.

6. The apparatus of claim 1 , further comprising an accelerator, the at least one cache memory operably coupled to the accelerator.

7. The apparatus of claim 1 , the logic to specify the cache status of the memory operation request via an agent class qualifier of the memory operation request.

8. The apparatus of claim 1 , the logic to use a snoop filter to perform the small cache coherence process.

9. The apparatus of claim 1 , the logic to use a directory field to perform the giant cache coherence process.

10. The apparatus of claim 1 , the memory operation request comprising a request to access a cache line, the cache status indicating the small cache status based on a copy of the cache line being stored in a small cache agent.

11. The apparatus of claim 1 , the memory operation request comprising a request to access a cache line, the cache status indicating the giant cache status based on a copy of the cache line being stored in a giant cache agent.

12. An apparatus, comprising:
at least one processor;
at least one cache memory;
a coherence controller having a snoop filter, the snoop filter comprising cache status information to indicate whether the at least one cache memory is a giant cache or a small cache; and
logic, at least a portion comprised in hardware, the logic to:
receive a memory operation request associated with the at least one cache memory,
determine a cache status of the memory operation request, the cache status indicating one of a giant cache status or a small cache status,
perform the memory operation request via a small cache coherence process responsive to a determination that the cache status is a small cache status, and
perform the memory operation request via a giant cache coherence process responsive to the determination that the cache status is a giant cache status.

13. A method, comprising:
storing a directory comprising cache status information to indicate whether at least one cache memory is a giant cache or a small cache;
receiving a memory operation request associated with the at least one cache memory;
determining a cache status of the memory operation request, the cache status indicating one of a giant cache status or a small cache status;
performing the memory operation request via a small cache coherence process responsive to the cache status being a small cache status; and
performing the memory operation request via a giant cache coherence process responsive to the cache status being a giant cache status.

14. The method of claim 13 , the at least one cache memory comprising at least one small cache and at least one giant cache.

15. The method of claim 13 , the at least one cache memory comprising at least one giant cache having a memory size greater than 1 gigabyte (GB).

16. The method of claim 13 , the at least one cache memory comprising at least one small cache having a memory size of less than or equal to 10 megabytes (MB).

17. The method of claim 13 , the memory operation request comprising a request to access a cache line, the cache status indicating the small cache status based on a copy of the cache line being stored in a small cache agent.

18. A method, comprising:
providing a snoop filter stored in a coherence controller of a computing device, the snoop filter comprising cache status information to indicate whether at least one cache memory is a giant cache or a small cache;
receiving a memory operation request associated with the at least one cache memory;
determining a cache status of the memory operation request, the cache status indicating one of a giant cache status or a small cache status;
performing the memory operation request via a small cache coherence process responsive to the cache status being a small cache status; and
performing the memory operation request via a giant cache coherence process responsive to the cache status being a giant cache status.

19. A non-transitory computer-readable storage medium that stores instructions for execution by processing circuitry of a computing device, the instructions to cause the computing device to:
store a directory comprising cache status information to indicate whether at least one cache memory is a giant cache or a small cache;
receive a memory operation request associated with the at least one cache memory;
determine a cache status of the memory operation request, the cache status indicating one of a giant cache status or a small cache status;
perform the memory operation request via a small cache coherence process responsive to a determination that the cache status is a small cache status; and
perform the memory operation request via a giant cache coherence process responsive to the determination that the cache status is a giant cache status.

20. The computer-readable storage medium of claim 19 , the at least one cache memory comprising at least one small cache and at least one giant cache.

21. The computer-readable storage medium of claim 19 , the at least one cache memory comprising at least one giant cache having a memory size greater than 1 gigabyte (GB).

22. The computer-readable storage medium of claim 19 , the at least one cache memory comprising at least one small cache having a memory size of less than or equal to 10 megabytes (MB).

23. A non-transitory computer-readable storage medium that stores instructions for execution by processing circuitry of a computing device, the instructions to cause the computing device to:
provide a snoop filter stored in a coherence controller of the computing device, the snoop filter comprising cache status information to indicate whether at least one cache memory is a giant cache or a small cache;
receive a memory operation request associated with the at least one cache memory;
determine a cache status of the memory operation request, the cache status indicating one of a giant cache status or a small cache status;
perform the memory operation request via a small cache coherence process responsive to a determination that the cache status is a small cache status; a

Assignees

• Intel Corp

Inventors

• Sankaran Rajesh
• Agarwal Ishwar
• Van Doren Stephen

Classifications

• G06F12/0817

  using directory methods · CPC title

• G06F12/0802 Primary

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/0833 Primary

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F12/0871

  Allocation or management of cache space · CPC title