Electronic device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11011548-B2
Application number	US-201916399227-A
Country	US
Kind code	B2
Filing date	Apr 30, 2019
Priority date	Dec 26, 2016
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

An electronic device includes a plurality of layers formed on a silicon-on-insulator (SOI) substrate. The SOI substrate includes a support substrate, a buried insulating layer formed on the support substrate, and a silicon layer formed on the buried insulating layer. A membrane structure of the electronic device includes the plurality of layers, the buried insulating later and the silicon layer but does not include the support substrate. A passivation film covers an upper surface and a side surface of the membrane structure.

First claim

The invention claimed is:

1. An electronic device, comprising:
(A) a membrane structure having an upper surface and side surfaces extending downwardly from the upper surface, the membrane structure including:
(i) a buried insulating layer having an upper surface;
(ii) a silicon layer covering a portion of the upper surface of the buried insulating layer, the silicon layer having an upper surface; and
(iii) a three layer wiring structure covering the upper surfaces of the buried insulating layer and the silicon layer, the three layer wiring structure including:
(a) a first interlayer insulating film located on the upper surfaces of the buried insulating layer and the silicon layer;
(b) a first wiring layer located on the first interlayer insulating film;
(c) a second interlayer insulating film covering the first wiring layer;
(d) a second wiring layer located on the second interlayer insulating film;
(e) a third interlayer insulating film covering the second wiring layer; and
(f) a third wiring layer located on the third interlayer insulating film; and

(B) a continuous passivation film formed on the upper surface and all of the side surfaces of the membrane structure so as to prevent, or at least reduce, entrance of gas and moisture through the outermost side surfaces of the membrane structure.

2. The electronic device according to claim 1 , further including contact plugs extending through respective ones of the interlayer insulating films and connecting respective ones of the wiring layers.

3. The electronic device according to claim 1 , wherein the passivation film is formed of a silicon nitride film.

4. The electronic device according to claim 3 , wherein the passivation film comprises a silicon oxide film formed on the upper and side surfaces of the membrane structure and a silicon nitride film formed on the silicon oxide film.

5. The electronic device according to claim 1 , wherein the passivation film comprises a silicon oxide film formed on the upper and side surfaces of the membrane structure and a silicon nitride film formed on the silicon oxide film.

6. The electronic device according to claim 1 , wherein the passivation film has a protrusion of 5 μm or less on the side surface of the membrane structure.

7. The electronic device according to claim 1 , wherein the upper surface of the membrane structure is the outermost upper surface of the membrane structure and the side surfaces of the membrane structure are the outermost side surfaces of the membrane structure.

8. The electronic device according to claim 1 , further including a support substrate on which the buried insulating layer is formed.

9. The electronic device according to claim 1 , wherein the passivation film is formed on all exposed portions of the upper surface and the entire side surfaces of the membrane structure.

10. An electronic device comprising:
(a) a membrane structure having an upper surface and side surfaces extending downwardly from the upper surface, the membrane structure including:
(i) a buried insulating layer having an upper surface;
(ii) a silicon layer covering a portion of the upper surface of the buried insulating layer, the silicon layer having an upper surface; and
(iii) a wiring structure which is in direct contact with the upper surfaces of both the buried insulating layer and the silicon layer; and

(b) a continuous passivation film formed on the upper surface and all of the side surfaces of the membrane structure so as to prevent, or at least reduce, entrance of gas and moisture through the outermost side surfaces of the membrane structure.

Assignees

• Murata Manufacturing Co

Inventors

• Izumitani Junko

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1908

  using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX] · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title