Systems and methods for mitigation of nonlinearity related phase noise degradations

Patent metadata

Field	Value
Publication number	US-11005481-B2
Application number	US-201816204109-A
Country	US
Kind code	B2
Filing date	Nov 29, 2018
Priority date	Nov 29, 2018
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

A phase locked loop (PLL) system for mitigating non-linear phase errors stemming from time-variant integral non-linearity of the LO feedback phase quantizer (TDC) is disclosed. The system includes a phase modulation circuit which is configured to generate a plurality of phase shifts for a reference signal; select a phase shift of the plurality of phase shifts and introduce the selected phase shift into the reference signal, thereby modulating the phase difference between the feedback and the reference signal. Alternatively, the above phase modulation can be applied on the feedback signal path, attaining equivalent results. TDC is configured to quantize the phase of the LO feedback signal relative to the shifted reference signal to generate a phase detection signal, effectively modulating the non-linearity contributed error away from the LO center frequency. The phase detection signal is then digitally compensated for the intentional fractional frequency shift to allow the PLL to generate LO signal the desired frequency.

First claim

What is claimed is:

1. A phase locked loop (PLL) system for mitigating non-linear phase errors, the system comprising:
a modulation circuit configured to generate a plurality of phase shifts, select a phase shift based on the plurality of phase shifts and introduce the selected phase shift into one of a reference signal and a feedback signal to generate a phase shifted signal, the phase shifted signal having a relative phase shift between the reference signal and the feedback signal; and
a time to digital converter (TDC) configured to generate a phase detection signal based on the phase shifted signal.

2. The system of claim 1 , wherein the modulation circuit is configured to generate a compensation signal based on the introduced selected phase shift.

3. The system of claim 2 , further comprising circuitry configured to combine the compensation signal with the phase detection signal.

4. The system of claim 1 , wherein the plurality of phase shifts include fractional phase shifts.

5. The system of claim 1 , wherein the modulation circuit is configured to derive a fractional frequency of the feedback signal and utilize the derived fractional frequency to generate the plurality of phase shifts.

6. The system of claim 1 , wherein the modulation circuit is configured to determine a fraction based on a frequency of the feedback signal and a frequency of the reference signal and use the determined fraction to generate the plurality of phase shifts.

7. The system of claim 1 , wherein the modulation circuit includes a plurality of series connected delay units that are selectively activated to provide the selected phase shift.

8. The system of claim 1 , wherein the modulation circuit is configured to perform a calibration and assign a digital code to a plurality of modulation states.

9. The system of claim 8 , wherein the modulation circuit is further configured to activate one or more of the plurality of modulation states to generate the plurality of phase shifts.

10. The system of claim 8 , wherein the modulation circuit is further configured to activate one or more of the plurality of modulation states to generate a compensation signal.

11. A method of operating a phase locked loop (PLL) comprising:
determining a fractional frequency of a feedback signal;
generating a plurality of fractional frequency shifts by a modulation circuit based on the fractional frequency;
selecting a fractional frequency shift from the plurality of fractional frequency shifts aimed at mitigating non-linear phase errors;
introducing the selected fractional frequency shift into one of a reference signal and the feedback signal to generate a phase modulated signal; and
generating a compensation signal based on the selected fractional frequency shift.

12. The method of claim 11 , wherein selecting the fractional frequency shift comprises selecting a shift that shifts the fractional frequency of the feedback signal from a bad fraction to a good fraction.

13. The method of claim 11 , further comprising compensating the phase modulated signal for the introduced fractional shift after quantizing a relative phase of the feedback signal by a time to digital converter (TDC).

14. The method of claim 11 , further comprising utilizing noise shaping techniques for introducing the selected fractional frequency shift.

15. A method for a phase locked loop (PLL) system, the method comprising:
generating a plurality of phase shifts using a modulation circuit;
selecting a phase shift based on the plurality of phase shifts, at the modulation circuit, for mitigating non-linear phase errors;
introducing the selected phase shift into one of a reference signal and a feedback signal to generate a phase shifted signal, the phase shifted signal having a relative phase shift between the reference signal and the feedback signal; and
generating a phase detection signal based on the phase shifted signal using a time to digital converter (TDC).

16. The method of claim 15 , further comprising generating a compensation signal at the modulation circuit, based on the introduced selected phase shift.

17. The method of claim 16 , further comprising combining the compensation signal with the phase detection signal.

18. The method of claim 15 , wherein the plurality of phase shifts include fractional phase shifts.

19. The method of claim 15 , further comprising deriving a fractional frequency of the feedback signal at the modulation circuit and utilizing the derived fractional frequency to generate the plurality of phase shifts.

20. The method of claim 15 , further comprising determining a fraction based on a frequency of the feedback signal and a frequency of the reference signal, at the modulation circuit and using the determined fraction to generate the plurality of phase shifts.

Assignees

• Apple Inc

Inventors

• Shumaker Evgeny
• Horovitz Gil

Classifications

• H04B1/40 Primary

  Circuits · CPC title

• H04L27/0014

  Carrier regulation (of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657) · CPC title

• H03L7/141

  the phase-locked loop controlling several oscillators in turn · CPC title

• H03L7/1806

  the frequency divider comprising a phase accumulator generating the frequency divided signal · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title