Time to digital converter with increased range and sensitivity

Patent metadata

Field	Value
Publication number	US-10108148-B1
Application number	US-201715488278-A
Country	US
Kind code	B1
Filing date	Apr 14, 2017
Priority date	Apr 14, 2017
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

Systems and methods are provided for converting time measurements to digital value representing phase. Such systems and methods use a ring oscillator to create a coarse measurement of the time difference between first and second rising edges of a modulated signal. A two-dimensional Vernier structure is used to create a fine resolution measurement of the error in the coarse measurement. The coarse and fine measurements are combined to calculate a digital time measurement. A digital time output is calculated as the difference in successive digital time measurements. An offset digital time output is calculated as a difference in a digital time output in relation to a carrier period offset. The offset digital time output is scaled and accumulated to calculate the integrated time signal. The integrated time signals are synchronized to the carrier frequency to output a series of final phase measurements.

First claim

The invention claimed is:

1. A method comprising:
receiving at a receive time-to-digital conversion (TDC) circuit a modulated signal; using a ring oscillator of the TDC circuit to obtain a coarse measurement of a rising edge of the modulated signal;
using a 2D Vernier comparator circuit of the TDC circuit to obtain a fine resolution measurement of a coarse measurement error representing a difference between a delayed rising edge signal and a delayed coarse measurement signal;
using the coarse measurement and the fine resolution measurement to obtain a digital time measurement; and,
determining a phase of the modulated signal based on the digital time measurement.

2. The method of claim 1 wherein obtaining the coarse measurement comprises using the rising edge of the modulated signal to latch output values of each of a plurality of inverters in the ring oscillator.

3. The method of claim 2 wherein obtaining the coarse measurement further comprises identifying a pulse-propagating inverter as an inverter having a non-inverted latched output value.

4. The method of claim 3 further comprising counting a number of complete oscillations of the ring oscillator.

5. The method of claim 4 wherein counting the number of complete oscillations of the ring oscillator comprises:
incrementing a first counter when an output of a first inverter of the ring oscillator changes state;
incrementing a second counter when an output of a second inverter of the ring oscillator changes state; and
selecting a count value from either the first counter or the second counter based upon a location of the pulse-propagating inverter in relation to the first inverter and the second inverter.

6. The method of claim 1 further comprising:
initiating the Vernier comparator circuit using the rising edge of the modulated signal; and
selecting a stop input for providing a delayed coarse measurement signal to the Vernier comparator circuit using a control logic circuit and a first multiplexer.

7. The method of claim 6 wherein the control logic circuit controls the multiplexer to select a comparator located a predetermined number of delay elements past a pulse-propagating inverter.

8. The method of claim 6 wherein the delayed coarse measurement signal is processed by a delay element and an exclusive OR gate to generate a trigger signal upon a rising edge of the delayed coarse measurement signal.

9. The method of claim 7 wherein initiating the Vernier comparator circuit using the rising edge of the modulated signal comprises delaying the rising edge of the modulated signal using a second multiplexer and a number of delay elements equal to the predetermined number of delay elements.

10. The method of claim 1 wherein calculating the fine resolution measurement of the coarse measurement error comprises:
propagating the rising edge of the modulated signal through a first line of delay elements;
propagating the delayed coarse measurement signal through a second line of delay elements, wherein the first line of delay elements is slower than the second line of delay elements;
determining a fine measurement point using a matrix of arbiters that is a smallest arbiter location in which the delayed coarse measurement signal propagating through the second line of delay elements arrives at the fine measurement point before the rising edge of the modulated signal propagating through the first line of delay elements; and
outputting the fine resolution measurement.

11. The method of claim 10 wherein calculating a digital time measurement comprises:
calculating a coarse measurement time as the time of a measured amount of complete oscillations of the ring plus a current propagation time; and
calculating a digital time measurement as a coarse measurement count ratio times the coarse measurement time minus the fine resolution measurement plus a calibration correction factor.

12. The method of claim 11 wherein calculating the phase of the modulated signal based on the digital time measurement comprises:
calculating a digital time output as a difference in successive digital time measurements;
determining an output time to write the phase of the modulated signal; calculating a offset digital time output;
scaling the offset digital time output to calculate a scaled digital time signal; and accumulating the scaled digital time signal.

13. The method of claim 12 wherein calculating the digital time output comprises:
subtracting a first digital time measurement from a second digital time measurement to calculate a period difference value; and
adding a counter wrapping value to the period difference value when the first digital time measurement is greater than the second digital time measurement.

14. The method of claim 12 wherein determining the output time to write the phase of the modulated signal comprises enabling an output write signal when the digital time output exceeds an output time threshold.

15. The method of claim 12 wherein calculating an offset digital time output comprises subtracting a carrier period offset from the digital time output.

16. An apparatus comprising:
a coarse measurement circuit configured to calculate a coarse measurement of a period of a modulated signal represented by a first rising edge signal and a second rising edge signal, wherein the first rising edge signal and the second rising edge signal are elements of the modulated signal;
a fine measurement circuit configured to calculate a fine resolution measurement of a coarse measurement error representing a difference between the second rising edge signal and a subsequent coarse measurement signal; and
a phase calculation circuit configured to calculate the phase of the modulated signal, wherein the phase calculation circuit includes:
an offset digital time output circuit to subtract a carrier period offset from the digital time output;
a scaling circuit to scale a offset digital time output; and
an accumulating circuit to accumulate an output signal from the scaling circuit.

17. The apparatus of claim 16 wherein the coarse measurement circuit comprises: a first set of one or more inverters connected to form a ring of inverters;
one or more flip-flops connected to each inverter output in the ring of inverters;
one or more counters connected to one or more of inverter outputs from the first set of inverters;
a first multiplexer which has inputs connected to the inverter outputs from the first set of one or more inverters;
a first exclusive-OR logic gate input connected to the first multiplexer output;
a second set of one or more inverters connected in succession in which the output of the last inverter in the second set of one or more inverters is connected to all inputs of a second multiplexer; and
a second exclusive-OR logic gate connected to the second multiplexer output.

18. The apparatus of claim 16 wherein the fine measurement circuit comprises: a set of one or more inverters forming a first line of delay elements;
a set of one or more inverters forming a second line of delay elements, wherein the first line of delay elements is slower than the second line of delay elements;
a matrix of latches equal to the number of inverters in the first line of delay elements times the number of inverters in the second line of delay elements;
a set of connections that connect each inverter output in the first line of delay elements to each first latch input in a column of the matrix of latches; and
a set of connections that connect each inverter output in the second line of delay eleme

Assignees

• Innophase Inc

Inventors

• Testi Nicolo

Classifications

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title