Semiconductor device with contamination improvement

Patent metadata

Field	Value
Publication number	US-11004973-B2
Application number	US-201916429567-A
Country	US
Kind code	B2
Filing date	Jun 3, 2019
Priority date	Aug 29, 2015
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
forming a first gate structure and a second gate structure over a substrate;
forming an etching stop layer over the first gate structure and between the first gate structure and the second gate structure;
forming a dielectric layer over the etching stop layer, over the first gate structure, and between the first gate structure and the second gate structure;
etching the dielectric layer and the etching stop layer to expose the first gate structure, wherein a portion of the dielectric layer between the first gate structure and the second gate structure has a concave top surface after the etching the dielectric layer and the etching stop layer to expose the first gate structure;
forming an interface layer over the first gate structure and over the concave top surface of the portion of the dielectric layer;
etching the interface layer to define an opening overlying the first gate structure, the opening re-exposing the first gate structure, wherein:
a spacer surrounds the first gate structure, and
the interface layer continues to overlie the spacer after the etching the interface layer is complete; and

replacing a dummy gate electrode of the first gate structure with a gate electrode through the opening.

2. The method of claim 1 , wherein the portion of the dielectric layer having the concave top surface is spaced apart from the first gate structure by the etching stop layer.

3. The method of claim 1 , comprising:
removing the interface layer after the replacing to expose the concave top surface.

4. The method of claim 3 , comprising:
forming a material layer over the concave top surface after the removing, wherein a top surface of the material layer is elevated at the same level with a top surface of the first gate structure.

5. The method of claim 3 , comprising:
forming a material layer over the concave top surface after the removing, wherein a ratio of a thickness of a thickest portion of the material layer to a pitch of the first gate structure and the second gate structure ranges from 1/30 to 1/80.

6. The method of claim 3 , comprising:
forming a material layer over the concave top surface after the removing, wherein the material layer is a metal.

7. The method of claim 1 , wherein the portion of the dielectric layer having the concave top surface overlies a first doped region adjacent the first gate structure and a second doped region adjacent the second gate structure, the first doped region separated from the second doped region by an isolation structure.

8. The method of claim 1 , comprising:
implanting a first dopant having a first conductivity type into the substrate to form a first doped region adjacent the first gate structure; and
implanting a second dopant having a second conductivity type, different than the first conductivity type, into the substrate to form a second doped region adjacent the second gate structure, wherein:
the forming a dielectric layer over the first gate structure and between the first gate structure and the second gate structure comprises forming the dielectric layer to overlie the first doped region and the second doped region, and
the portion of the dielectric layer having the concave top surface overlies the first doped region and the second doped region.

9. The method of claim 1 , wherein the interface layer has a first etch selectivity and the dummy gate electrode has a second etch selectivity different than the first etch selectivity.

10. The method of claim 1 , wherein the etching the dielectric layer and the etching stop layer comprises performing a chemical mechanical polishing process to concurrently etch the dielectric layer and the etching stop layer.

11. The method of claim 1 , wherein after the etching the dielectric layer and the etching stop layer, a top surface of the dielectric layer, a top surface of the etching stop layer, and a top surface of the first gate structure are co-planar.

12. A method of forming a semiconductor device, comprising:
forming a first gate structure and a second gate structure over a substrate;
forming an etching stop layer between the first gate structure and the second gate structure;
forming a dielectric layer over the etching stop layer and between the first gate structure and the second gate structure, wherein:
the dielectric layer has a concave top surface, and
the dielectric layer is spaced apart from the first gate structure by the etching stop layer;

forming an interface layer over the first gate structure and over the dielectric layer;
etching the interface layer to define an opening overlying the first gate structure, wherein the opening is defined by the first gate structure and an exposed sidewall of the interface layer;
replacing a dummy gate electrode of the first gate structure with a gate electrode through the opening; and
replacing the interface layer with a material layer after the replacing a dummy gate electrode, wherein the material layer is a metal.

13. The method of claim 12 , wherein:
the forming an etching stop layer comprises forming the etching stop layer over the first gate structure, and
the forming a dielectric layer comprises forming the dielectric layer over the first gate structure.

14. The method of claim 13 , comprising:
planarizing the dielectric layer and the etching stop layer to expose a top surface of the first gate structure.

15. The method of claim 12 , wherein the replacing the interface layer comprises:
removing the interface layer after the replacing a dummy gate electrode to expose the concave top surface; and
forming the material layer over the concave top surface after the removing.

16. The method of claim 15 , wherein the forming a material layer comprises:
forming the material layer such that a top surface of the material layer is elevated at the same level with a top surface of the first gate structure.

17. A method of forming a semiconductor device, comprising:
forming a first gate structure over a first device region of a substrate between a first doped region and a second doped region of the first device region and forming a second gate structure over a second device region of the substrate between a first doped region and a second doped region of the second device region, wherein the first device region is separated from the second device region by an isolation structure;
forming an etching stop layer over the substrate, over the first gate structure, and peripherally surrounding the first gate structure;
forming an interlayer dielectric layer over the etching stop layer;
removing a portion of the etching stop layer overlying the first gate structure after the forming an interlayer dielectric layer;
replacing a dummy gate electrode of the first gate structure with a gate electrode after the removing; and
forming a material layer over the interlayer dielectric layer after the replacing a dummy gate electrode, wherein:
at a smallest distance between the material layer and the first gate structure, the material layer is separated from the first gate structure by the etching stop layer and a spacer disposed between the first gate structure and the etching stop layer,
the material layer has a top surface which is elevated at the same level with a top surface of the first gate structure, and
the material layer is a metal.

18. The method of claim 17 , wherein a ratio of a thickness of a thickest portion of the material layer to a pitch of the first gate structure and the second gate struct

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Sun Chung-Ren
• Jangjian Shiu-Ko
• Chen Kun-Ei
• Lin Chun-Che

Classifications

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/071

  of dielectric parts thereof · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title