Method for manufacturing semiconductor device with contamination improvement

Patent metadata

Field	Value
Publication number	US-9722076-B2
Application number	US-201514839932-A
Country	US
Kind code	B2
Filing date	Aug 29, 2015
Priority date	Aug 29, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions disposed in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
providing a substrate having at least two device regions separated by at least one isolation structure which is disposed in the substrate;
forming two dummy gate structures on the device regions respectively, wherein each of the dummy gate structures comprises a dummy gate electrode;
forming a plurality of doped regions in the substrate, wherein each of the device regions comprises two of the doped regions disposed at two opposite sides of each of the dummy gate structures;
forming an interlayer dielectric layer on the substrate to peripherally surround the dummy gate structures, wherein tops of the dummy gate electrodes are exposed;
forming an interface layer on the interlayer dielectric layer and the dummy gate structures, wherein a material forming the interface layer is different from a material forming the interlayer dielectric layer, and the interface layer is formed to contact the tops of the dummy gate electrodes;
forming a plurality of openings in the interface layer to expose the tops of the dummy gate electrodes;
replacing the dummy gate electrodes with two gate electrodes;
removing the interface layer; and
forming a material layer on the interlayer dielectric layer, wherein the material layer has a top surface which is elevated at the same level with the tops of the gate electrodes, and a ratio of a thickness of a thickest portion of the material layer to a pitch of the gate electrodes ranges from 1/30 to 1/80.

2. The method of claim 1 , wherein forming the dummy gate structures comprises forming each of the dummy gate structures comprising a gate dielectric layer underlying the dummy gate electrode.

3. The method of claim 1 , wherein between forming the dummy gate structures and forming the doped regions, the method further comprising forming two spacers peripherally surrounding the dummy gate structures respectively.

4. The method of claim 3 , wherein between forming the spacers and forming the interlayer dielectric layer, the method further comprising forming an etching stop layer to cover the substrate, the at least one isolation structure, the doped regions, the spacers and the dummy gate structures.

5. The method of claim 4 , wherein forming the interlayer dielectric layer comprises:
forming an interlayer dielectric material layer on the etching stop layer to cover the substrate and the dummy gate structures; and
performing a planarization step on the interlayer dielectric material layer to remove a portion of the interlayer dielectric material layer and a portion of the etching stop layer to form the interlayer dielectric layer and expose the tops of the dummy gate electrodes.

6. The method of claim 1 , wherein forming the interface layer is performed using a deposition process, an implant process, a plasma treatment process, or an oxidization process.

7. The method of claim 6 , wherein the deposition process is a selective atomic layer deposition process.

8. The method of claim 6 , wherein the plasma treatment process is performed using nitrogen as a working gas.

9. The method of claim 6 , wherein the oxidization process is performed using hydrogen peroxide (H 2 O 2 ), tartaric acid (C 4 H 6 O 6 ), or citric acid (C 6 H 8 O 7 ) as an oxidant.

10. The method of claim 1 , wherein replacing the dummy gate electrodes with the gate electrodes comprises:
removing the dummy gate electrodes to form two cavities in the interlayer dielectric layer;
forming a gate material layer to fill the cavities and to cover the interface layer; and
performing a chemical mechanical polishing process on the gate material layer to remove a portion of the gate material layer to form the gate electrodes and expose the interface layer.

11. The method of claim 1 , wherein a ratio of the thickness of the thickest portion of the material layer to a thickness of a thickest portion of the interlayer dielectric layer is greater than 0 and smaller than 1/30.

12. The method of claim 1 , wherein the interface layer is formed from silicon dioxide, silicon nitride, or silicon oxynitride.

13. A method for manufacturing a semiconductor device, the method comprising:
providing a substrate having at least two device regions separated by at least one isolation structure which is disposed in the substrate;
forming two dummy gate structures on the device regions respectively, wherein each of the dummy gate structures comprises a dummy gate electrode;
forming two spacers on the substrate to peripherally surround the dummy gate structures respectively;
forming a plurality of doped regions in the substrate, wherein each of the device regions comprises two of the doped regions disposed at two opposite sides of each of the dummy gate structures;
forming an etching stop layer to cover the substrate, the doped regions, the spacers, and the dummy gate structures;
forming an interlayer dielectric material layer to cover the etching stop layer;
performing a planarization step on the interlayer dielectric material layer to remove a portion of the interlayer dielectric material layer and a portion of the etching stop layer to form an interlayer dielectric layer and expose tops of the dummy gate electrodes;
forming an interface layer on the interlayer dielectric layer and the tops of the dummy gate electrodes, wherein a material forming the interface layer is different from a material forming the interlayer dielectric layer, and the interface layer is formed to contact the tops of the dummy gate electrodes;
forming a plurality of openings in the interface layer to respectively expose the tops of the dummy gate electrodes;
removing the dummy gate electrodes to form two cavities in the interlayer dielectric layer;
forming a gate material layer to fill the cavities and to cover the interface layer;
performing a chemical mechanical polishing process on the gate material layer to remove a portion of the gate material layer to form two gate electrodes in the cavities and expose the interface layer;
removing the interface layer; and
forming a material layer on the interlayer dielectric layer, wherein the material layer has a top surface which is elevated at the same level with the tops of the gate electrodes, and a ratio of a thickness of a thickest portion of the material layer to a pitch of the gate electrodes ranges from 1/30 to 1/80.

14. The method of claim 13 , wherein forming the interface layer is performed using a deposition process, an implant process, a plasma treatment process, or an oxidization process.

15. The method of claim 14 , wherein the plasma treatment process is performed using nitrogen as a working gas.

16. The method of claim 14 , wherein the oxidization process is performed using hydrogen peroxide (H 2 O 2 ), tartaric acid (C 4 H 6 O 6 ), or citric acid (C 6 H 8 O 7 ) as an oxidant.

17. The method of claim 13 , wherein a ratio of the thickness of the thickest portion of the material layer to a thickness of a thickest portion of the interlayer dielectric layer is greater than 0 and smaller than 1/30.

18. A method for manufacturing a semiconductor device, the method comprising:
providing a substrate having at least two device regions separated by at least one isolation structure which is disposed in the substrate;
forming two dummy gate structures on the device regions respectively, wherein each of the dummy gate structures comprises a dummy gate electrode;
forming a plurality of doped regions in the substrate, wherein each of the device regions compri

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Manufacturning Co Ltd

Inventors

• Sun Chung-Ren
• Jangjian Shiu-Ko
• Chen Kun-Ei
• Lin Chun-Che

Classifications

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/071

  of dielectric parts thereof · CPC title

• H01L29/6656

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic