Semiconductor device having multiple gate pads

Patent metadata

Field	Value
Publication number	US-11004841-B2
Application number	US-201916379609-A
Country	US
Kind code	B2
Filing date	Apr 9, 2019
Priority date	Apr 12, 2016
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

Disclosed are semiconductor devices that include additional gate pads, and methods of fabricating and testing such devices. A device may include a first gate pad, a second gate pad, and a third gate pad. The first gate pad is connected to a gate including a gate oxide layer. The second and third gate pads are part of an electro-static discharge (ESD) protection network for the device. The ESD protection network is initially isolated from the first gate pad and hence from the gate and gate oxide layer. Accordingly, gate oxide integrity (GOI) testing can be effectively performed and the reliability and quality of the gate oxide layer can be checked. The second gate pad can be subsequently connected to the first gate pad to enable the ESD protection network, and the third gate pad can be subsequently connected to an external terminal when the device is packaged.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a gate comprising a gate oxide layer;
a source terminal;
a drain terminal;
a first gate pad coupled to a substrate and also coupled to the source and drain terminals and to the gate, wherein the first gate pad receives a first voltage during gate oxide integrity (GOI) testing, and wherein the first voltage is greater than the rated operational voltage of the gate oxide layer;
a second gate pad coupled to the substrate, wherein the second gate pad comprises a portion of an electro-static discharge (ESD) protection network for the semiconductor device and is electrically isolated from the first gate pad at all times during the GOI testing, and wherein the ESD protection network is electrically isolated from the first gate pad and the first voltage during the GOI testing;
a third gate pad coupled to the substrate, wherein the third gate pad also comprises a portion of the ESD protection network and is electrically isolated from the first gate pad at all times during the GOI testing, and wherein the first gate pad occupies less area of the semiconductor device than the third gate pad, and wherein the second gate pad occupies less area of the semiconductor device than the third gate pad; and
an anti-fuse disposed between and coupled to the first and second gate pads, wherein an electrical connection is formed between the first and second gate pads in response to a voltage that is applied to the anti-fuse, to enable the ESD protection network and to also enable a connection between the gate of the semiconductor device and a terminal that is external to the semiconductor device.

2. The semiconductor device of claim 1 , further comprising a wire bond that connects the third gate pad and a terminal that is external to the semiconductor device.

3. The semiconductor device of claim 1 , wherein the substrate comprises a wafer having a plurality of other semiconductor devices formed thereon, wherein the first gate pad is electrically isolated from the second gate pad and from the third gate pad.

4. The semiconductor device of claim 1 , further comprising a wire bond connecting the source terminal and a terminal that is external to the semiconductor device.

5. The semiconductor device of claim 1 , wherein the ESD protection network is selected from the group consisting of: a two-stage ESD network comprising a resistor and at least two Zener diodes; and a one-stage ESD network comprising a Zener diode.

6. The semiconductor device of claim 1 , comprising a vertical device comprising a metal-oxide-semiconductor field-effect transistor (MOSFET).

7. A method of fabricating a semiconductor device, the method comprising:
forming a gate on a substrate, the gate comprising a gate oxide layer;
forming a first gate pad coupled to the gate, wherein the first gate pad is operable for receiving a first voltage during gate oxide integrity (GOI) testing, and wherein the first voltage is greater than the rated operational voltage of the gate oxide layer;
forming a source terminal coupled to the first gate pad;
forming a drain terminal coupled to the first gate pad;
forming a second gate pad coupled to the substrate, wherein the second gate pad comprises a portion of an electro-static discharge (ESD) protection network for the semiconductor device and is configured to be electrically isolated from the first gate pad at all times during the GOI testing, and wherein the ESD protection network is configured to be electrically isolated from the first gate pad and the first voltage during the GOI testing;
forming a third gate pad coupled to the substrate, wherein the third gate pad also comprises a portion of the ESD protection network and is electrically isolated from the first gate pad at all times during the GOI testing, wherein the first gate pad occupies less area of the semiconductor device than the third gate pad, and wherein the second gate pad occupies less area of the semiconductor device than the third gate pad; and
forming an anti-fuse disposed between and coupled to the first and second gate pads, wherein an electrical connection is formed between the first and second gate pads in response to a voltage that is applied to the anti-fuse, to enable the ESD protection network and to also enable a connection between the gate of the semiconductor device and a terminal that is external to the semiconductor device.

8. The method of claim 7 , further comprising forming a wire bond that connects the third gate pad and a terminal that is external to the semiconductor device.

9. The method of claim 7 , wherein the substrate comprises a wafer having a plurality of other semiconductor devices formed thereon, wherein the first gate pad is electrically isolated from the second gate pad and from the third gate pad.

10. The method of claim 7 , wherein the ESD protection network is selected from the group consisting of: a two-stage ESD network comprising a resistor and at least two Zener diodes; and a one-stage ESD network comprising a Zener diode.

11. The method of claim 7 , wherein the semiconductor device comprises a vertical device comprising a metal-oxide-semiconductor field-effect transistor (MOSFET).

Assignees

• Vishay Siliconix
• Vishay Siliconix Llc

Inventors

• Park Chanho
• Shibib Ayman
• Terrill Kyle

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/5453

  connecting between multiple bond pads on a chip, e.g. daisy chain · CPC title

• H10W72/019

  of bond pads · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title