Control system, semiconductor device and method of the semiconductor device

Patent metadata

Field	Value
Publication number	US-11004830-B2
Application number	US-201916598806-A
Country	US
Kind code	B2
Filing date	Oct 10, 2019
Priority date	Nov 21, 2018
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

The control system according to embodiments includes a switching element, a control unit controlling the conductive state of the switching element, and a first capacitor storing charge supplied to the control unit. The first capacitor and the control unit are connected with each other via the switching element.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first chip having a first surface; and
a second chip having a second surface,
wherein the second chip comprises a capacitor and a switching element,
wherein the first chip comprises a control unit configured to control a conductive state of the switching element,
wherein the control unit is connected with the capacitor via the switching element by laminating the first surface and the second surface with each other,
wherein the control unit includes a clock generation circuit configured to generate a clock signal for an operation of the control unit,
wherein the first chip comprises:
a first interlayer insulating film; and
a first electrode pad formed in the first interlayer insulating film, the first electrode pad forming a part of the first surface,

wherein the second chip comprises:
a second interlayer insulating film; and
a second electrode pad formed in the second interlayer insulating film, the second electrode pad forming a part of the second surface, and

wherein the first electrode pad and the second electrode pad are laminated with each other.

2. The semiconductor device according to claim 1 , wherein the switching element is an IGZO transistor.

3. The semiconductor device according to claim 2 , wherein the switching element is formed at a position closer to the second surface than the capacitor.

4. The semiconductor device according to claim 1 , comprising a power generating element electrically connected with the control unit.

5. The semiconductor device according to claim 4 , wherein the power generating element is electrically connected with the capacitor via the switching element.

6. The semiconductor device according to claim 4 , wherein the power generating element is a solar cell, a piezoelectric element, or a peltier element.

7. The semiconductor device according to claim 4 , wherein the power generating element is electrically connected with the control unit and the capacitor via a diode.

8. A method of manufacturing a semiconductor device, the method comprising:
forming a first chip having a first surface;
forming a second chip having a second surface; and
laminating the first surface and the second surface with each other,
wherein the second chip comprises a capacitor and a switching element,
wherein the first chip comprises a control unit controlling a conductive state of the switching element,
wherein the control unit is connected with the capacitor via the switching element by laminating the first surface and the second surface with each other,
wherein the switching element is an IGZO transistor, and
wherein the switching element is formed in the forming the second chip after the forming the capacitor.

Assignees

• Renesas Electronics Corp

Inventors

• Kuwabara Shinichi
• Nakashiba Yasutaka
• Iida Tetsuya

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W72/019

  of bond pads · CPC title