Microelectronic device including fiber-containing build-up layers

Patent metadata

Field	Value
Publication number	US-11004792-B2
Application number	US-201816145804-A
Country	US
Kind code	B2
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

Described are microelectronic devices including a substrate formed with multiple build-up layers, and having at least one build-up layer formed of a fiber-containing material. A substrate can include a buildup layers surrounding an embedded die, or outward of the build-up layer surrounding the embedded die that includes a fiber-containing dielectric. Multiple build-up layers located inward from a layer formed of a fiber-containing dielectric will be formed of a fiber-free dielectric.

First claim

The invention claimed is:

1. A microelectronic device, comprising:
a substrate comprising multiple build-up layers, each build-up layer including a dielectric and supporting an associated conductive layer extending over the dielectric and forming contacts extending through the dielectric; and
an embedded die extending within a recess in a selected build-up layer, the embedded die electrically engaging contacts of an adjacent build-up layer, wherein the contacts of the adjacent build-up layer that engage the embedded die are located within a dielectric without fibers;
wherein at least one of the selected build-up layer and an additional build-up layer located outward of the selected build-up layer includes a dielectric comprising fibers, and
wherein multiple build-up layers located inward from the selected build-up layer each include a dielectric without fibers.

2. The microelectronic device of claim 1 , wherein the selected build-up layer forming the recess includes a dielectric comprising fibers.

3. The microelectronic device of claim 2 , wherein one or more build-up layers located outward of the selected build-up layer includes dielectric without fibers.

4. The microelectronic device of claim 1 , wherein the selected build-up layer including the recess includes a dielectric without, fibers, and wherein an additional build-up layer extending outward of the selected build-up layer includes a dielectric comprising glass fibers.

5. The microelectronic device of claim 1 , wherein the substrate includes a core, and wherein all build-up layers located between a first side of the core and the selected build-up layer include a dielectric without fibers.

6. The microelectronic device of claim 1 , wherein the fibers comprise glass fibers.

7. The microelectronic device of claim 1 wherein the dielectric comprising fibers comprises a prepreg material.

8. The microelectronic device of claim 1 wherein the dielectric comprising fibers comprises a build-up material with glass cloth.

9. The microelectronic device of claim 1 , wherein the substrate is a cureless substrate.

10. The microelectronic device of claim 2 , wherein the embedded die is housed within a recess formed in the dielectric of the selected build-up layer.

11. The microelectronic device of claim 4 , wherein the additional build-up layer dielectric with glass fibers defines an open region above the embedded die and wherein the open region is filled with a dielectric without fibers.

12. The microelectronic device of claim 1 , further comprising a first external die coupled to the substrate, and electrically coupled to the embedded die.

13. The microelectronic device of claim 12 , further comprising a second external die coupled to the substrate and electrically coupled to the embedded die, and wherein the embedded die is a bridge die interconnecting the first and second external die.

14. The microelectronic device of claim 13 , wherein electrical contacts formed in the build-up layer comprising fibers are placed at a first minimum pitch; and wherein electrical contacts to the embedded die are placed at a second minimum pitch, the second minimum pitch smaller than the first minimum pitch.

15. A microelectronic device, comprising:
a substrate comprising multiple build-up layers, each build-up layer including a dielectric and supporting an associated conductive layer extending over the dielectric and forming contacts extending through the dielectric; and
wherein at least a first outermost buildup layer of the substrate is formed of a material comprising build-up material with glass cloth;
wherein multiple adjacent build-up layers located inward from the outermost build-up layer each include a dielectric without fibers; and
wherein contacts in build-up layers with fibers include contacts spaced at a first minimum pitch, and wherein contacts in build-up layers without fibers include contacts spaced at a second minimum pitch smaller than the first minimum pitch.

16. The microelectronic device of claim 15 , wherein a second outermost buildup layer on an opposite side of the substrate is formed of a material comprising build-up material with glass cloth.

17. An electronic system, comprising:
a microelectronic device, comprising,
a substrate comprising,
multiple build-up layers, each build-up layer including a dielectric, and supporting an associated conductive layer extending over the dielectric and forming contacts extending through the dielectric; and
an embedded die extending within a recess in a selected build-up layer, the embedded die electrically engaging contacts of an adjacent build-up layer, wherein the contacts of the adjacent build-up layer that engage the embedded die are located within a dielectric without fibers;
wherein at least one of the selected build-up layer and an additional build-up layer located outward of the selected build-up layer includes a dielectric comprising fibers, and
wherein multiple adjacent build-up layers located inward from the selected build-up layer each include a dielectric without fibers;

a surface semiconductor die extending above the substrate and electrically coupled to the embedded die; and
at least one of another microelectronic device, a mass storage device and a network interface operably coupled to the microelectronic device.

18. The electronic system of claim 17 , wherein the dielectric comprising fibers comprises glass fibers in an organic matrix.

Assignees

• Intel Corp

Inventors

• Chavali Sri Chaitra Jyotsna

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W72/951

  Materials of bond pads · CPC title

• H10W72/077

  Connecting of TAB connectors · CPC title

• H10W70/22

  having an heterogeneous or anisotropic structure · CPC title