Semiconductor device with a multi-layered encapsulant and associated systems, devices, and methods

Patent metadata

Field	Value
Publication number	US-11004697-B2
Application number	US-201916436461-A
Country	US
Kind code	B2
Filing date	Jun 10, 2019
Priority date	Nov 17, 2017
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

First claim

We claim:

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate including traces, wherein the traces protrude above a top surface of the substrate;
forming a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces and the top surface of the substrate;
attaching an interim structure to the substrate over the prefill material, wherein the interim structure includes:
a die including a bottom surface,
pillars protruding from the die for electrically coupling to the traces,
solder contacting the pillars opposite the die, and
a wafer-level underfill between the die and the prefill material and directly contacting the bottom surface of the die and the pillars, wherein the wafer-level underfill includes material that, at least under an initial state, reflows with the solder;

curing at least one of the wafer-level underfill and the prefill material, with the wafer-level underfill and the prefill material persisting as separate layers after curing.

2. The method of claim 1 wherein forming the prefill material includes applying a nonconductive paste (NCP) between the traces.

3. The method of claim 2 wherein applying the NCP includes applying the NCP including a fluxing function or trait.

4. The method of claim 2 wherein applying the NCP includes applying the NCP with a top surface of the NCP coplanar with or above top surfaces of the traces.

5. The method of claim 2 wherein:
applying the NCP includes applying the NCP directly contacting at least a portion of one or more top surfaces of the traces;
attaching the interim structure includes removing the NCP from at least a portion of one or more top surfaces of the traces based on a fluxing function associated with the NCP.

6. The method of claim 2 wherein attaching the interim structure includes attaching the interim structure without curing the NCP.

7. The method of claim 2 further comprising at least partially curing the NCP before attaching the interim structure.

8. The method of claim 2 wherein forming the prefill material includes jetting the a nonconductive liquid encapsulant between the traces.

9. The method of claim 4 wherein jetting the nonconductive liquid encapsulant includes using a high precision jetting process for controlling a location in jetting the nonconductive liquid encapsulant, a volume of the nonconductive liquid encapsulant at the location, or a combination thereof.

10. The method of claim 9 wherein jetting the nonconductive liquid encapsulant includes keeping the nonconductive liquid encapsulant away from top surfaces of the traces.

11. The method of claim 8 wherein jetting the nonconductive liquid encapsulant includes jetting the nonconductive liquid encapsulant with a top surface thereof coplanar with or below top surfaces of one or more of the traces.

12. The method of claim 8 further comprising at least partially curing the nonconductive liquid encapsulant before attaching the interim structure.

13. The method of claim 8 wherein attaching the interim structure includes attaching the interim structure without curing the nonconductive liquid encapsulant.

14. The method of claim 1 further comprising assembling the interim structure including:
providing the die including pillars extending from a bottom surface of the die;
forming solder bumps on the pillars opposite the die; and
laminating the wafer-level underfill directly contacting the bottom surface and pillars.

15. The method of claim 14 wherein attaching the interim structure includes reflowing the solder bumps and the wafer-level underfill, wherein the solder bumps directly contact the traces and the pillars and the wafer-level underfill directly contacts the prefill material.

Assignees

• Micron Technology Inc

Inventors

• Luo Shijian
• Hacker Jonathan S

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title