Reduction operation mapping systems and methods

Patent metadata

Field	Value
Publication number	US-11003446-B2
Application number	US-201715842343-A
Country	US
Kind code	B2
Filing date	Dec 14, 2017
Priority date	Jul 14, 2017
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

Adder trees may be constructed for efficient packing of arithmetic operators into an integrated circuit. The operands of the trees may be truncated to pack an integer number of nodes per logic array block. As a result, arithmetic operations may pack more efficiently onto the integrated circuit while providing increased precision and performance.

First claim

What is claimed is:

1. An integrated circuit having an adder tree configured to generate a sum based at least in part on an output and an additional value, the adder tree comprising:
first input circuitry configured to receive a first operand, wherein the first operand comprises a first plurality of bits;
second input circuitry configured to receive a second operand, wherein the second operand comprises a second plurality of bits;
soft logic circuitry configured to separate one or more bits from the first plurality of bits to generate a first subset operand and configured to separate an additional one or more bits from the second plurality of bits to generate a second subset operand;
adder circuitry configured to generate the output based at least in part the first subset operand and the second subset operand; and
additional circuitry configured to generate the additional value based at least in part on the one or more bits.

2. The integrated circuit of claim 1 , wherein the additional circuitry comprises a trailing adder tree, wherein the trailing adder tree comprises additional adder circuitry configured to generate the additional value based at least in part on a summation of the one or more bits and the additional one or more bits.

3. The integrated circuit of claim 2 , wherein the trailing adder tree is configured to separate a bit from the one or more bits to generate a subset of the one or more bits, and, wherein the additional adder circuitry is configured to generate the additional value based at least in part on a summation of the subset of the one or more bits and the additional one or more bits.

4. The integrated circuit of claim 1 , wherein the additional circuitry is configured to generate the additional value based in part on a distribution of possible values of the one or more bits.

5. The integrated circuit of claim 1 , wherein the soft logic circuitry comprises the additional circuitry and is configured to generate the additional value by emulating constant compression of the additional value.

6. The integrated circuit of claim 1 , wherein the soft logic circuitry comprises a look up table configured to generate the additional value based in part on the one or more bits.

7. The integrated circuit of claim 1 , wherein the one or more bits comprise one or more least significant bits.

8. The integrated circuit of claim 1 , wherein the adder tree is configured to append the additional value to the output, prepend the additional value to the output, or a combination thereof.

9. The integrated circuit of claim 1 , wherein the adder tree is configured to generate the sum based at least in part on a summation of the additional value and the output.

10. The integrated circuit of claim 1 , wherein the adder tree is configured to perform a multiplication operation of a multiplicand and a multiplier, wherein the first operand comprises the multiplicand, wherein the second operand comprises the multiplier, wherein the adder circuitry is configured to generate the output based at least in part on a first partial product of the first subset operand and the second subset operand and a second partial product of the first subset operand and the second subset operand, and, wherein the additional circuitry is configured to generate the additional value based at least in part on a first least significant bit of a third partial product of the multiplicand and the multiplier and a second least significant bit of a fourth partial product of the multiplicand and the multiplier.

11. The integrated circuit of claim 10 , wherein the sum comprises a product of the multiplication operation, and wherein the additional value comprises a carry-in value to the output.

12. The integrated circuit of claim 1 , wherein the one or more bits comprise one or more most significant bits.

13. The integrated circuit of claim 12 , wherein the one or more most significant bits comprise one or more sign bits, and, wherein the additional value comprises a sign bit decoded based in part on the one or more bits and the additional one or more bits.

Assignees

• Intel Corp

Inventors

• Langhammer Martin
• Baeckler Gregg William
• Pasca Bogdan

Classifications

• G06F7/509 Primary

  for multiple operands, e.g. digital integrators · CPC title

• G06F2207/4824

  Neural networks · CPC title

• G06F7/523

  Multiplying only · CPC title

• G06F7/485

  Adding; Subtracting {(G06F7/4833, G06F7/4836 take precedence)} · CPC title

• G06F7/501 Primary

  Half or full adders, i.e. basic adder cells for one denomination · CPC title