Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10998432-B2
Application number	US-201916673425-A
Country	US
Kind code	B2
Filing date	Nov 4, 2019
Priority date	Jul 27, 2017
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

A semiconductor device including an IE-type trench gate IGBT requires to be improved in IE effect to reduce on voltage. The semiconductor device includes a trench gate electrode or a trench emitter electrode between an active cell region and an inactive cell region. The trench gate electrode and the trench emitter electrode are provided across the inactive cell region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate having a first main surface and a second main surface on a side opposite to the first main surface;
a first semiconductor region having a first conductivity type and provided in the semiconductor substrate;
a second semiconductor region having a second conductivity type different from the first conductivity type and provided in the semiconductor substrate between the first semiconductor region and the first main surface;
a third semiconductor region having the second conductivity type and provided in the semiconductor substrate between the first semiconductor region and the second main surface;
a first trench penetrating the second semiconductor region;
a second trench provided away from the first trench while penetrating the second semiconductor region;
a fourth semiconductor region having the first conductivity type and provided on a side close to the first main surface in the second semiconductor region so as to be in contact with a first side surface of the first trench, and located between the first trench and the second trench;
a first trench electrode provided over an inside of the first trench with a first insulating film in between;
a second trench electrode provided over an inside of the second trench with a second insulating film as in between;
a fifth semiconductor region having the second conductivity type and formed in the first semiconductor region in a portion located on a side opposite to the fourth semiconductor region across the first trench;
a sixth semiconductor region having the second conductivity type formed in the first semiconductor region in a portion located on a side opposite to the fourth semiconductor region across the second trench; and
a contact hole in contact with the second trench and the fourth semiconductor region.

2. The semiconductor device according to claim 1 , further comprising a seventh semiconductor region having the first conductivity type and formed in the first semiconductor region in a portion located between the first trench and the second trench, wherein concentration of an impurity having the first conductivity type in the seventh semiconductor region is higher than concentration of an impurity having the first conductivity type in the first semiconductor region, and lower than concentration of an impurity having the first conductivity type in the fourth semiconductor region.

3. The semiconductor device according to claim 1 , wherein depth of each of the fifth and sixth semiconductor regions from the first main surface is deeper than depth of each of the first trench and the second trench from the first main surface.

4. The semiconductor device according to claim 2 , further comprising:
a third trench penetrating the second semiconductor region in a portion located on a side opposite to the first trench across the fifth semiconductor region;
a fourth trench penetrating the second semiconductor region in a portion located on a side opposite to the second trench across the sixth semiconductor region;
a first coupling trench provided so as to be coupled to the first trench and the fourth trench, and extending in a first direction in planar view;
a first end trench provided between the first trench and the fourth trench so as to be coupled to the second trench, and extending in the first direction in planar view;
a third trench electrode provided over an inside of the third trench with an insulating film in between;
a fourth trench electrode provided over an inside of the fourth trench with an insulating film in between;
a first trench coupling electrode provided over an inside of the first coupling trench with an insulating film in between;
a first trench end electrode provided over an inside of the first end trench with an insulating film in between; and
an eighth semiconductor region having the first conductivity type and running from the first main surface to a depth of a bottom of the first coupling trench between the first coupling trench and the first end trench,
wherein the first trench electrode, the second trench electrode, the third trench electrode, and the fourth trench electrode are provided away from one another in a first direction and extend in a second direction orthogonal to the first direction in planar view, and
wherein concentration of an impurity having the first conductivity type in the eighth semiconductor region is higher than the concentration of the impurity having the first conductivity type in the first semiconductor region, and lower than the concentration of the impurity having the first conductivity type in the fourth semiconductor region.

5. The semiconductor device according to claim 4 , further comprising:
a second end trench running up to the first semiconductor region, and provided between the first trench and the fourth trench so as to be coupled to the first end trench, and extending in the second direction in planar view;
a second trench end electrode provided over an inside of the second end trench with an insulating film in between; and
the eighth semiconductor region provided between the fourth trench and the second end trench.

6. The semiconductor device according to claim 2 , further comprising:
a third trench penetrating the second semiconductor region in a portion located on a side opposite to the first trench across the fifth semiconductor region;
a fourth trench penetrating the second semiconductor region in a portion located on a side opposite to the second trench across the sixth semiconductor region;
a first coupling trench provided so as to be coupled to the first trench and the third trench, and extending in a first direction in planar view;
a second coupling trench provided so as to be coupled to the second trench and the fourth trench, and extending in the first direction in planar view;
a fifth trench having a frame shape in planar view, and provided between the first trench, the third trench, and the first coupling trench while penetrating the second semiconductor region in the fifth semiconductor region;
a third trench electrode provided over an inside of the third trench with an insulating film in between;
a fourth trench electrode provided over an inside of the fourth trench with an insulating film in between;
a fifth trench electrode provided over an inside of the fifth trench with an insulating film in between;
a first trench coupling electrode provided over an inside of the first coupling trench with an insulating film in between;
a second trench coupling electrode provided over an inside of the second coupling trench with an insulating film in between; and
a contact hole in contact with the fifth trench and the second semiconductor region;
wherein the first trench electrode, the second trench electrode, the third trench electrode, and the fourth trench electrode are provided away from one another in a first direction and extend in a second direction orthogonal to the first direction.

7. The semiconductor device according to claim 2 , further comprising:
a third trench penetrating the second semiconductor region in a portion located on a side opposite to the first trench across the fifth semiconductor region;
a fourth trench penetrating the second semiconductor region in a portion located on a side opposite to the second trench across the sixth semiconductor region;
a fifth trench penetrating the second semiconductor region in a portion located on a side opposite to the second trench across the fourth trench;
a sixth trench and a seventh trench provided so as to be coupled to the second trench and the fourth trench, and provided away from each other in a second direction while extending in a first direction in planar view;
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Assignees

• Renesas Electronics Corp

Inventors

• Nagata Nao

Classifications

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H10D64/23

  Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/378

  Contact regions to the substrate regions · CPC title