One transistor and ferroelectric FET based memory cell

Patent metadata

Field	Value
Publication number	US-10998339-B2
Application number	US-201616347085-A
Country	US
Kind code	B2
Filing date	Dec 12, 2016
Priority date	Dec 12, 2016
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

Described herein are ferroelectric memory cells and corresponding methods and devices. For example, in some embodiments, a ferroelectric memory cell disclosed herein includes one access transistor and one ferroelectric transistor (1T-1FE-FET cell). The access transistor is coupled to the ferroelectric transistor by sharing its source/drain terminal with that of the ferroelectric transistor and is used for both READ and WRITE access to the ferroelectric transistor.

First claim

The invention claimed is:

1. An apparatus, comprising:
an access transistor; and
a ferroelectric transistor, comprising a ferroelectric material between a gate electrode material of the ferroelectric transistor and a channel material of the ferroelectric transistor,
wherein,
a ferroelectric transistor terminal pair includes a source terminal and a drain terminal of the ferroelectric transistor,
an access transistor terminal pair includes a source terminal and a drain terminal of the access transistors,
a first terminal of the ferroelectric transistor terminal pair is coupled to a first terminal of the access transistor terminal pair, and
either the channel material of the ferroelectric transistor is shaped as a fin extending away from a substrate and the gate electrode material of the ferroelectric transistor wraps around the fin, or the channel material of the ferroelectric transistor is shaped as a wire disposed over the substrate and the gate electrode material of the ferroelectric transistor wraps around the wire.

2. The apparatus according to claim 1 , wherein a gate terminal of the access transistor is coupled to a word-line (WL).

3. The apparatus according to claim 1 , wherein a gate terminal of the ferroelectric transistor is coupled to a ferroelectric-line (FL).

4. The apparatus according to claim 1 , wherein a second terminal of the ferroelectric transistor terminal pair is coupled to a source-line (SL).

5. The apparatus according to claim 1 , wherein a second terminal of the access transistor terminal pair is coupled to a bit-line (BL).

6. The apparatus according to claim 1 , wherein the access transistor includes the ferroelectric material between a gate electrode material of the access transistor and a channel material of the access transistor.

7. The apparatus according to claim 6 , wherein:
the channel material of the access transistor is shaped as a fin extending away from a substrate and the gate electrode material of the access transistor wraps around the fin, or
the channel material of the access transistor is shaped as a wire provided over the substrate and the gate electrode material of the access transistor wraps around the wire.

8. The apparatus according to claim 1 , wherein the ferroelectric material has a thickness between 1 nanometers and 10 nanometers.

9. The apparatus according to claim 1 , wherein the ferroelectric material includes one or more of hafnium zirconium oxide, silicon-doped hafnium oxide, germanium-doped hafnium oxide, aluminum-doped hafnium oxide, and yttrium-doped hafnium oxide.

10. The apparatus according to claim 1 , wherein the access transistor and the ferroelectric transistor are a part of a memory cell, and the memory cell is one of a plurality of memory cells of the apparatus.

11. The apparatus according to claim 10 , wherein the apparatus is a memory array.

12. An apparatus, comprising:
an access transistor; and
a ferroelectric transistor,
wherein:
a ferroelectric transistor terminal pair includes a source terminal and a drain terminal of the ferroelectric transistor,
an access transistor terminal pair includes a source terminal and a drain terminal of the access transistor,
a first terminal of the ferroelectric transistor terminal pair is coupled to a first terminal of the access transistor terminal pair,
the ferroelectric transistor includes a ferroelectric material between a gate electrode material of the ferroelectric transistor and a channel material of the ferroelectric transistor, and
the ferroelectric material has a thickness between 1 nanometers and 10 nanometers.

13. The apparatus according to claim 12 , wherein the access transistor includes the ferroelectric material between a gate electrode material of the access transistor and a channel material of the access transistor.

14. The apparatus according to claim 13 , wherein:
the channel material of the access transistor is shaped as a fin extending away from a substrate and the gate electrode material of the access transistor wraps around the fin, or
the channel material of the access transistor is shaped as a wire provided over the substrate and the gate electrode material of the access transistor wraps around the wire.

15. The apparatus according to claim 12 , wherein the access transistor and the ferroelectric transistor are a part of a memory cell, and the memory cell is one of a plurality of memory cells of the apparatus.

16. The apparatus according to claim 12 , wherein the apparatus is a memory array.

17. An apparatus, comprising:
an access transistor; and
a ferroelectric transistor,
wherein:
a ferroelectric transistor terminal pair includes a source terminal and a drain terminal of the ferroelectric transistor,
an access transistor terminal pair includes a source terminal and a drain terminal of the access transistor,
a first terminal of the ferroelectric transistor terminal pair is coupled to a first terminal of the access transistor terminal pair, and
a second terminal of the access transistor terminal pair is coupled to a sense amplifier configured to sense a logic state programmed in the ferroelectric transistor.

18. The apparatus according to claim 17 , further comprising a bit-line (BL), wherein the second terminal of the access transistor terminal pair is coupled to the sense amplifier by the second terminal of the access transistor terminal pair being coupled to the BL and the BL being coupled to the sense amplifier.

19. The apparatus according to claim 17 , wherein:
the ferroelectric transistor includes a ferroelectric material between a gate electrode material of the ferroelectric transistor and a channel material of the ferroelectric transistor, and
either the channel material of the ferroelectric transistor is shaped as a fin extending away from a substrate and the gate electrode material of the ferroelectric transistor wraps around the fin, or the channel material of the ferroelectric transistor is shaped as a wire disposed over the substrate and the gate electrode material of the ferroelectric transistor wraps around the wire.

20. The apparatus according to claim 17 , wherein:
the access transistor and the ferroelectric transistor are a part of a memory cell,
the memory cell is one of a plurality of memory cells of the apparatus, and
the apparatus is a memory array.

Assignees

• Intel Corp

Inventors

• Morris Daniel H
• Avci Uygar E
• Young Ian A

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title