End of life performance throttling to prevent data loss

Patent metadata

Field	Value
Publication number	US-10998066-B2
Application number	US-201916589956-A
Country	US
Kind code	B2
Filing date	Oct 1, 2019
Priority date	Oct 31, 2017
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

Disclosed in some examples are methods, systems, memory devices, machine readable mediums configured to intentionally degrade NAND performance when a value of a NAND health metric indicates a potential for failure to encourage users to replace or backup their devices before data loss occurs. For example, the system may track a NAND health metric and when that metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may be more effective than a warning to effect device backup or replacement.

First claim

The invention claimed is:

1. A memory device comprising:
a memory array comprising multiple memory cells;
a memory controller configured to perform operations comprising:
monitoring an operational metric of the memory device;
determining whether the operational metric meets a specified condition, the specified condition indicating a memory device degradation;
responsive to determining that the operational metric meets the specified condition, slowing down, by the memory controller, a performance of the memory device;
receiving a host request;
determining whether the host request corresponds to a backup operation; and
responsive to determining that the host request corresponds to the backup operation, refraining from slowing down, by the memory controller, the performance of the memory device when servicing the host request.

2. The memory device of claim 1 , wherein the operations of slowing down, by the memory controller, the performance of the memory device comprises lowering an operating frequency of one of the memory controller.

3. The memory device of claim 1 , wherein the operations of slowing down, by the memory controller, the performance of the memory device comprises introducing an intentional delay when servicing at least one of a read request or a write request.

4. The memory device of claim 1 , wherein the operations of determining whether the host request corresponds to the backup operation comprises comparing an amount of pending read requests to a defined threshold; and
wherein the operations of determining that the host request corresponds to the backup operation comprises determining that the amount of pending read requests exceeds the defined threshold.

5. The memory device of claim 1 , wherein the operational metric comprises a number of bad blocks.

6. The memory device of claim 1 , wherein the operational metric comprises an overprovisioning metric.

7. The memory device of claim 1 , wherein the operational metric comprises a read error metric.

8. The memory device of claim 1 , wherein the operations comprises a write error metric.

9. The memory device of claim 1 , wherein the operational metric comprises at least two of: a number of bad blocks, an overprovisioning metric, a read error metric, or a write metric.

10. A method of controlling a memory device, the method comprising:
monitoring an operational metric of the memory device;
determining whether the operational metric meets a specified condition, the specified condition indicating a memory device degradation; and
responsive to determining that the operational metric meets the specified condition, slowing down, by a memory controller, a performance of the memory device;
receiving a host request;
determining whether the host request corresponds to a backup operation; and
responsive to determining that the host request corresponds to the backup operation, refraining from slowing down, by the memory controller, the performance of the memory device when servicing the host request.

11. The method of claim 10 , wherein slowing down, by the memory controller, the performance of the memory device comprises lowering an operating frequency of one of the memory controller.

12. The method of claim 10 , wherein slowing down, by the memory controller, the performance of the memory device comprises introducing an intentional delay when servicing at least one of a read request or a write request.

13. The method of claim 10 , wherein determining whether the host request corresponds to the backup operation comprises comparing an amount of pending read requests to a defined threshold; and
wherein determining that the host request corresponds to the backup operation comprises determining that the amount of pending read requests exceeds the defined threshold.

14. The method of claim 10 , wherein the operational metric comprises a number of bad blocks.

15. The method of claim 10 , wherein the operational metric comprises an overprovisioning metric.

16. The method of claim 10 , wherein the operational metric comprises a read error metric.

17. The method of claim 10 , wherein the operational metric comprises a write error metric.

18. The method of claim 10 , wherein the operational metric comprises at least two of: a number of bad blocks, an overprovisioning metric, a read error metric, or a write metric.

Assignees

• Micron Technology Inc

Inventors

• Jean Sebastien Andre

Classifications

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1044 Primary

  with specific ECC/EDC distribution · CPC title

• G11C16/32

  Timing circuits · CPC title