End of life performance throttling to prevent data loss

Patent metadata

Field	Value
Publication number	US-10453543-B2
Application number	US-201715799577-A
Country	US
Kind code	B2
Filing date	Oct 31, 2017
Priority date	Oct 31, 2017
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

Disclosed in some examples are methods, systems, memory devices, machine readable mediums configured to intentionally degrade NAND performance when a value of a NAND health metric indicates a potential for failure to encourage users to replace or backup their devices before data loss occurs. For example, the system may track a NAND health metric and when that metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may be more effective than a warning to effect device backup or replacement.

First claim

The invention claimed is:

1. A NAND memory device comprising:
a NAND memory array including a first pool of memory; and
a controller, the controller executing instructions, to cause the controller to perform operations comprising:
monitoring a NAND device health metric;
determining that the NAND device health metric meets a degradation criteria indicating NAND device degradation has already occurred; and
responsive to determining that the NAND device health metric meets the degradation criteria, degrading a performance of the NAND memory device.

2. The NAND memory device of claim 1 , wherein the operations of degrading the performance of the NAND memory device comprises degrading a particular characteristic of the NAND memory device.

3. The NAND memory device of claim 2 , wherein the particular characteristic is a write speed, and wherein the operations of degrading the performance of the NAND does not include degrading a read speed.

4. The NAND memory device of claim 2 , wherein the particular characteristic is a read speed, and wherein the operations of degrading the performance of the NAND does not include degrading a write speed.

5. The NAND memory device of claim 2 , wherein the particular characteristic is a read and a write speed.

6. The NAND memory device of claim 1 , wherein the operations of degrading the performance of the NAND memory device comprises introducing a delay before servicing a host request.

7. The NAND memory device of claim 1 , wherein the operations of degrading the performance of the NAND memory device comprises degrading the performance of the NAND memory device an amount that is based upon the NAND device health metric.

8. The NAND memory device of claim 1 , wherein the NAND device health metric is a number of bad blocks, and wherein the amount of performance degradation increases as the amount of bad blocks increase.

9. The NAND memory device of claim 1 , wherein the operations further comprise
detecting a host activity that matches a backup profile; and
responsive to detecting the host activity that matches the backup profile, suspending the degradation of the performance of the NAND device while the host activity matches the backup profile.

10. The NAND memory device of claim 9 , wherein the backup profile comprises a read queue depth that is greater than a predetermined amount.

11. A method comprising:
at a controller of a NAND memory device:
monitoring a NAND device health metric of the NAND memory device;
determining that the NAND device health metric meets a degradation criteria indicating NAND device degradation has already occurred; and
responsive to determining that the NAND device health metric meets the degradation criteria, degrading a performance of the NAND memory device.

12. The method of claim 11 , wherein degrading the performance of the NAND memory device comprises degrading a particular characteristic of the NAND memory device.

13. The method of claim 12 , wherein the particular characteristic is a write speed, and wherein degrading the performance of the NAND does not include degrading a read speed.

14. The method of claim 12 , wherein the particular characteristic is a read speed, and wherein degrading the performance of the NAND does not include degrading a write speed.

15. The method of claim 11 , wherein degrading the performance of the NAND memory device comprises introducing a delay before servicing a host request.

16. A non-transitory machine-readable medium, comprising instructions, which when executed by a machine, causes the machine to perform operations comprising:
at a controller of a NAND memory device:
monitoring a NAND device health metric;
determining that the NAND device health metric meets a degradation criteria indicating NAND device degradation has already occurred; and
responsive to determining that the NAND device health metric meets the degradation criteria, degrading a performance of the NAND memory device.

17. The non-transitory machine-readable medium of claim 16 , wherein the operations of degrading the performance of the NAND memory device comprises degrading a particular characteristic of the NAND memory device.

18. The non-transitory machine-readable medium of claim 17 , wherein the particular characteristic is a write speed, and wherein the operations of degrading the performance of the NAND does not include degrading a read speed.

19. The non-transitory machine-readable medium of claim 7 , wherein the particular characteristic is a read speed, and wherein the operations of degrading the performance of the NAND does not include degrading a write speed.

20. The non-transitory machine-readable medium of claim 16 , wherein the NAND device health metric is a number of bad blocks, and wherein the amount of performance degradation increases as the amount of bad blocks increase.

21. The non-transitory machine-readable medium of claim 16 , wherein the operations further comprise:
detecting a host activity that matches a backup profile; and
responsive to detecting the host activity that matches the backup profile, suspending the degradation of the performance of the NAND device while the host activity matches the backup profile.

Assignees

• Micron Technology Inc

Inventors

• Jean Sebastien Andre

Classifications

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title