Shift register unit, driving method thereof, gate driving circuit, and display device

Patent metadata

Field	Value
Publication number	US-10319325-B2
Application number	US-201715718100-A
Country	US
Kind code	B2
Filing date	Sep 28, 2017
Priority date	Feb 23, 2017
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

The embodiments of the present disclosure provides a shift register unit, a driving method thereof, a gate driving circuit and a display device, which relate to the field of display technology. The shift register unit includes a pull-up control module, a reset module, a pull-up module, a pull-down control module and a pull-down module, wherein the pull-down control module is configured to pull a voltage level of the pull-down node down to the second voltage terminal under control of the pull-up node, or the pull-down control module is configured to store a voltage of the third voltage terminal and output a voltage of the third voltage terminal to the pull-down node or release the stored voltage to the pull-down node under control of the third voltage terminal and the second voltage terminal.

First claim

What is claimed is:

1. A shift register unit, comprising a pull-up control module, a reset module, a pull-up module, a pull-down control module and a pull-down module, wherein:
the pull-up control module is connected to a first voltage terminal, a signal input terminal and a pull-up node, and the pull-up control module is configured to output a voltage of the first voltage terminal to the pull-up node under control of the signal input terminal;
the reset module is connected to a reset signal terminal, a second voltage terminal, and the pull-up node, and the reset module is configured to pull a voltage level of the pull-up node down to a voltage of the second voltage terminal under control of the reset signal;
the pull-up module is connected to the pull-up node, a clock signal terminal and a signal output terminal, and the pull-up module is configured to output a signal of the clock signal terminal to the signal output terminal under control of the pull-up node;
the pull-down control module is connected to the second voltage terminal, a third voltage terminal, the pull-up node and a pull-down node, and the pull-down control module is configured to pull a voltage level of the pull-down node down to the voltage of the second voltage terminal under control of the pull-up node, or the pull-down control module is configured to store a voltage of the third voltage terminal and output the voltage of the third voltage terminal to the pull-down node or release the stored voltage to the pull-down node under control of the third voltage terminal and the second voltage terminal;
the pull-down module is connected to the pull-down node, the pull-up node, the signal output terminal and the second voltage terminal, and the pull-down module is configured to pull the voltage level of the pull-up node and a voltage level of the signal output terminal down to the voltage of the second voltage terminal under control of the pull-down node;
wherein the pull-down control module comprises a first transistor, a second transistor and a first capacitor;
a gate electrode of the first transistor is connected to the pull-up node, a first electrode of the first transistor is connected to the third voltage terminal, and a second electrode of the first transistor is connected to a first end of the first capacitor;
a second end of the first capacitor is connected to the second voltage terminal; and
a gate electrode of the second transistor is connected to the pull-up node, a first electrode of the second transistor is connected to the pull-down node, and a second electrode of the second transistor is connected to the second voltage terminal; and
wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor; or the first transistor is an N-type transistor and the second transistor is a P-type transistor.

2. The shift register unit according to claim 1 , further comprising a reconfiguring module connected to a fourth voltage terminal, the second voltage terminal and the signal output terminal, and the reconfiguring module is configured to pull the voltage level of the signal output terminal down to the voltage of the second voltage terminal under control of the fourth voltage terminal.

3. The shift register unit according to claim 2 , wherein the reconfiguring module comprises an eighth transistor, a gate electrode of the eighth transistor is connected to the fourth voltage terminal, a first electrode of the eighth transistor is connected to the signal output terminal and a second electrode of the eighth transistor is connected to the second voltage terminal.

4. The shift register unit according to claim 1 , wherein the pull-up module comprises a third transistor and a second capacitor;
a gate electrode of the third transistor is connected to the pull-up node, a first electrode of the third transistor is connected to the clock signal terminal and a second electrode of the third transistor is connected to the signal output terminal; and
a first end of the second capacitor is connected to the gate electrode of the third transistor and a second end of the second capacitor is connected to a second electrode of the third transistor.

5. The shift register unit according to claim 1 , wherein the pull-up control module comprises a fourth transistor, a gate electrode of the fourth transistor is connected to the signal input terminal, a first electrode of the fourth transistor is connected to the first voltage terminal and a second electrode of the fourth transistor is connected to the pull-up node.

6. The shift register unit according to claim 1 , wherein the reset module comprises a fifth transistor, a gate electrode of the fifth transistor is connected to the reset signal terminal, a first electrode of the fifth transistor is connected to the pull-up node and a second electrode of the fifth transistor is connected to the second voltage terminal.

7. The shift register unit according to claim 1 , wherein the pull-down module comprises a sixth transistor and a seventh transistor;
a gate electrode of the sixth transistor is connected to the pull-down node, a first electrode of the sixth transistor is connected to the pull-up node and a second electrode of the sixth transistor is connected to the second voltage terminal; and
a gate electrode of the seventh transistor is connected to the pull-down node, a first electrode of the seventh transistor is connected to the signal output terminal, and a second electrode of the seventh transistor is connected to the second voltage terminal.

8. A gate driving circuit, comprising a plurality of cascaded shift register units according to claim 1 , wherein
a signal input terminal of a first stage shift register unit is connected to a start signal terminal;
except for the first stage shift register unit, a signal output terminal of a previous stage shift register unit is connected to a signal input terminal of a next stage shift register unit;
except for a last stage shift register unit, a signal output terminal of the next stage shift register unit is connected to a reset signal terminal of the previous stage shift register unit; and
a reset signal terminal of the last stage shift register unit is connected to the start signal terminal.

9. The gate driving circuit according to claim 8 , further comprising a reconfiguring module connected to a fourth voltage terminal, the second voltage terminal and the signal output terminal, and the reconfiguring module is configured to pull the voltage level of the signal output terminal down to the voltage of the second voltage terminal under control of the fourth voltage terminal.

10. The gate driving circuit according to claim 9 , wherein the reconfiguring module comprises an eighth transistor, a gate electrode of the eighth transistor is connected to the fourth voltage terminal, a first electrode of the eighth transistor is connected to the signal output terminal and a second electrode of the eighth transistor is connected to the second voltage terminal.

11. The gate driving circuit of claim 8 , wherein the pull-up module comprises a third transistor and a second capacitor;
a gate electrode of the third transistor is connected to the pull-up node, a first electrode of the third transistor is connected to the clock signal terminal and a second electrode of the third transistor is connected to the signal output terminal; and
a first end of the second capacitor is connected to the gate electrode of the third transistor and a second end of the second capacitor is connected to a second electrode of the third transistor.

12. The gate driving circuit according to claim 8 , wherein the pull-up control modu

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Xu Fei

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G3/3655

  Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title