Additional spacer for self-aligned contact for only high voltage FinFETs

Patent metadata

Field	Value
Publication number	US-10991689-B2
Application number	US-201916376234-A
Country	US
Kind code	B2
Filing date	Apr 5, 2019
Priority date	Apr 5, 2019
Publication date	Apr 27, 2021
Grant date	Apr 27, 2021

Abstract

A method includes forming a first region including a pair of first FinFETs and a second region including a pair of second FinFETs on a substrate. Each FinFET includes a metal gate having a first spacer adjacent thereto, and each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET, such that the first FinFETs can be higher voltage input/output devices. The method forms a first contact between the metal gates of the pair of first FinFETs with a second spacer thereabout, the second spacer contacting a portion of each first spacer. The second spacer thus has a portion extending parallel to the metal gates, and a portion extending perpendicular to the metal gates. A second contact is formed between the metal gates of the pair of second FinFETs, and the second contact devoid of the second spacer.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first region including a pair of first fin-type field effect transistors (FinFETs) on a substrate;
a second region including a pair of second FinFETs on the substrate, each of the first FinFETs and the second FinFETs including a metal gate having a first spacer extending linearly along each side of the metal gate, and wherein each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET;
a second spacer adjacent to a portion of each first spacer of the pair of first FinFETs and adjacent to an interlayer dielectric between the pair of first FinFETs;
a first contact extending between the metal gates of the pair of first FinFETs to a first source/drain region, the first contact completely surrounded by the second spacer such that the first contact is free of contact with the interlayer dielectric; and
a second contact extending between the metal gates of the pair of second FinFETs to a second source/drain region, the second contact in contact with the first spacer adjacent the metal gates of the pair of second FinFETs.

2. The IC of claim 1 , wherein each first FinFET has a higher breakdown voltage than each second FinFET.

3. The IC of claim 1 , wherein each first spacer is linear and extends along a respective metal gate, and wherein each second spacer includes portions extending linearly along a portion of respective first spacers and portions extending perpendicularly between adjacent first spacers.

4. The IC of claim 3 , wherein each second spacer surrounds a respective first contact.

5. The IC of claim 1 , wherein the second spacer has a dielectric constant of less than 4.0.

6. The IC of claim 1 , wherein the second spacer includes silicon oxy-carbide (SiOC) or silicon oxy-carbonitride (SiOCN).

7. The IC of claim 1 , wherein the second spacer has at least one first portion extending parallel to the metal gates, and at least one second portion extending perpendicular to the metal gates.

8. The IC of claim 3 , wherein the portions of each second spacer extending linearly along the portion of respective first spacers of the pair of first FinFETs are adjacent to and in contact with the portion of respective first spacers and the first contact, and the portions of each second spacer extending perpendicularly between adjacent first spacers of the pair of first FinFETs are adjacent to and in contact with the interlayer dielectric and the first contact.

9. The IC of claim 1 , wherein the first contact is free of contact with the interlayer dielectric and the first spacer of the pair of first FinFETs.

10. The IC of claim 1 , wherein the second contact is adjacent to and in contact with the interlayer dielectric and the first spacer of the pair of second FinFETs.

11. An integrated circuit, comprising:
a first region including a pair of first fin-type field effect transistors (FinFETs) on a substrate;
a second region including a pair of second FinFETs on the substrate, each FinFET including a metal gate having a first spacer extending linearly along each side of the metal gate, and wherein each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET;
a second spacer adjacent to a portion of each first spacer of the pair of first FinFETs, wherein the second spacer is adjacent to and in contact with an interlayer dielectric between the pair of first FinFETs;
a first contact extending between the metal gates of the pair of first FinFETs to a first source/drain region, the first contact surrounded by the second spacer; and
a second contact extending between the metal gates of the pair of second FinFETs to a second source/drain region, the second contact in contact with the first spacer adjacent the metal gates of the pair of second FinFETs.

12. The IC of claim 11 , wherein each first FinFET has a higher breakdown voltage than each second FinFET.

13. The IC of claim 11 , wherein each first spacer is linear and extends along a respective metal gate, and wherein each second spacer includes portions extending linearly along a portion of respective first spacers and portions extending perpendicularly between adjacent first spacers.

14. The IC of claim 13 , wherein the portions of each second spacer extending linearly along the portion of respective first spacers of the pair of first FinFETs are adjacent to and in contact with the portion of respective first spacers and the first contact, and the portions of each second spacer extending perpendicularly between adjacent first spacers of the pair of first FinFETs are adjacent to and in contact with the interlayer dielectric and the first contact.

15. The IC of claim 11 , wherein each second spacer surrounds a respective first contact.

16. The IC of claim 11 , wherein the second spacer has a dielectric constant of less than 4.0.

17. The IC of claim 11 , wherein the second spacer includes silicon oxy-carbide (SiOC) or silicon oxy-carbonitride (SiOCN).

18. The IC of claim 11 , wherein the second spacer has at least one first portion extending parallel to the metal gates, and at least one second portion extending perpendicular to the metal gates.

19. The IC of claim 11 , wherein the first contact is free of contact with the interlayer dielectric and the first spacer of the pair of first FinFETs.

20. The IC of claim 11 , wherein the second contact is adjacent to and in contact with the interlayer dielectric and the first spacer of the pair of second FinFETs.

Assignees

• Globalfoundries Us Inc

Inventors

• Zainuddin Abu Naser M
• Sheraw Christopher D
• Saudari Sangameshwar Rao
• Ma Wei
• Zhao Kai
• Haran Bala S

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title