System, method, and computer program product for grouping one or more failures in a formal verification
US-10599797-B1 · Mar 24, 2020 · US
US10990735B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10990735-B2 |
| Application number | US-202016882671-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 25, 2020 |
| Priority date | May 25, 2019 |
| Publication date | Apr 27, 2021 |
| Grant date | Apr 27, 2021 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A system and method generates cluster-based power architecture interfaces for an integrated circuit (IC) design under test (DUT) debugging by receiving design data for an IC DUT, determining power characteristic data for the IC DUT, generating display components within a graphical user interface (GUI) corresponding to individual components encompassed within a power intent hierarchy corresponding with the IC DUT, generating graphical links between displayed components, overlaying interactive elements corresponding with generated violation clusters over graphical links, and providing root-cause interactive elements within the generated GUI having visual associations with the interactive components corresponding with particular violation clusters.
Opening claim text (preview).
That which is claimed: 1. A system for generating a cluster-based power architecture interface, the system comprising: a memory storage device; a processor configured to: receive design data for an integrated circuit (IC) design; determine, based at least in part on the design data, power characteristic data for the IC design, wherein the power characteristic data identifies a power intent hierarchy for the IC design and violations present within the IC design; generate within a graphical user interface (GUI), display components corresponding to individual components encompassed within the power intent hierarchy; generate, within the GUI and based at least in part on the design data, one or more graphical links between displayed components; generate, based at least in part on the power characteristic data for the IC design, one or more violation clusters each comprising a plurality of design violations for the IC design, wherein design violations within each of the one or more violation clusters are characterized as having at least one shared root cause; associate the one or more violation clusters with the one or more graphical links; overlay a plurality of interactive elements over the GUI, wherein the plurality of interactive elements comprise: at least one interactive link element providing data indicative of the one or more violation clusters in association with corresponding ones of the one or more graphical links; at least one root-cause element corresponding to the at least one shared root cause; and a graphical association between the at least one interactive link element and the at least one root-cause element to indicate a relationship between the at least one root-cause element and the at least one interactive link element. 2. The system for generating a cluster-based power architecture interface of claim 1 , wherein the at least one interactive link element has associated detail data indicative of individual violations within a violation cluster, and wherein the processor is configured to: upon receipt of input indicating interaction with a first interactive element, display a detail element within the GUI comprising at least a portion of the detail data. 3. The system for generating a cluster-based power architecture interface of claim 2 , wherein the detail data comprises a plurality of interactive links associated with individual violations within the violation cluster, and wherein the processor is additionally configured to: upon receipt of input indicating interaction with an interactive link associated with a first individual violation, display a detail-view GUI providing a violation-specific schematic associated with the first individual violation. 4. The system for generating a cluster-based power architecture interface of claim 1 , wherein: the display components comprise source components and sink components; and each of the one or more graphical links directly links at least one source component with at least one sink component. 5. The system for generating a cluster-based power architecture interface of claim 1 , wherein the at least one root-cause element comprises primary root-cause elements and secondary root-cause elements, and wherein at least one primary root-cause element is visually linked with at least one secondary root-cause element to demonstrate the at least one primary root-cause element being a cause of the at least one secondary root-cause element. 6. The system for generating a cluster-based power architecture interface of claim 1 , wherein the GUI comprises the display components in a hierarchical arrangement, wherein display components corresponding to individual components are displayed within one of a common source parent boundary or a common sink parent boundary, and wherein the GUI displays the common source parent boundary and the common sink parent boundary within a common parent boundary. 7. The system for generating a cluster-based power architecture interface of claim 1 , wherein: determining power characteristic data for the IC DUT comprises generating a tabular power characteristic reference table for each violation cluster; and overlaying a plurality of interactive elements over the GUI comprises generating the at least one interactive link element based at least in part on the tabular power characteristic reference table for each cluster. 8. A computer-implemented method for generating a cluster-based power architecture interface, the method comprising: receiving, via one or more processors, design data for an integrated circuit (IC) design; determining, based at least in part on the design data, power characteristic data for the IC design, wherein the power characteristic data identifies a power intent hierarchy for the IC design and violations present within the IC design; generating within a graphical user interface (GUI), display components corresponding to individual components encompassed within the power intent hierarchy; generating, within the GUI and based at least in part on the design data, one or more graphical links between displayed components; generating, based at least in part on the power characteristic data for the IC design, one or more violation clusters each comprising a plurality of design violations for the IC design, wherein design violations within each of the one or more violation clusters are characterized as having at least one shared root cause; associating the one or more violation clusters with the one or more graphical links; overlaying a plurality of interactive elements over the GUI, wherein the plurality of interactive elements comprise: at least one interactive link element providing data indicative of the one or more violation clusters in association with corresponding ones of the one or more graphical links; at least one root-cause element corresponding to the at least one shared root cause; and a graphical association between the at least one interactive link element and the at least one root-cause element to indicate a relationship between the at least one root-cause element and the at least one interactive link element. 9. The computer-implemented method for generating a cluster-based power architecture interface of claim 8 , wherein the at least one interactive link element has associated detail data indicative of individual violations within a violation cluster, and wherein the method further comprises: upon receipt of input indicating interaction with a first interactive element, displaying a detail element within the GUI comprising at least a portion of the detail data. 10. The computer-implemented method for generating a cluster-based power architecture interface of claim 9 , wherein the detail data comprises a plurality of interactive links associated with individual violations within the violation cluster, and wherein the method further comprises: upon receipt of input indicating interaction with an interactive link associated with a first individual violation, displaying a detail-view GUI providing a violation-specific schematic associated with the first individual violation. 11. The computer-implemented method for generating a cluster-based power architecture interface of claim 8 , wherein: the display components comprise source components and sink components; and each of the one or more graphical links directly links at least one source component with at least one sink component. 12. The computer-implemented method for generating a cluster-based power architecture interface of claim 8 , wherein the at least one root-cause element comprises primary root-cause elements and secondary root-cause elements, and wherein at least one pr
Power grid distribution networks · CPC title
Design verification, e.g. functional simulation or model checking · CPC title
Interaction techniques to control parameter settings, e.g. interaction with sliders or dials · CPC title
using formal methods, e.g. equivalence checking or property checking · CPC title
Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.