Orthogonal differential vector signaling

Patent metadata

Field	Value
Publication number	US-10985806-B2
Application number	US-201916511911-A
Country	US
Kind code	B2
Filing date	Jul 15, 2019
Priority date	Apr 30, 2010
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

Using a transformation based at least in part on a non-simple orthogonal or unitary matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmission and acquisition points, and/or that has a pin-efficiency that is greater than 50% and may approach that of single-ended signaling. Such transformations may be implemented in hardware in an efficient manner. Hybrid transformers that apply such transformations to selected subsets of signals to be transmitted may be used to adapt to various signal set sizes and/or transmission environment properties including noise and physical space requirements of given transmission environments.

First claim

What is claimed is:

1. A method comprising:
obtaining a sequence of binary data bits representing information;
generating a set of signals from the sequence of binary data bits, each signal generated responsive to a weighted summation of the sequence of binary data bits, each binary data bit weighted according to a respective row of a set of rows of a non-simple orthogonal or unitary matrix, the set of rows (i) mutually orthogonal and (ii) the set of rows excludes a row consisting entirely of ones;
transmitting the set of signals as a plurality of analog voltages on respective wires of a multi-wire bus; and
generating a set of outputs representing the information, each output of the set of outputs generated by forming a respective analog linear combination of the plurality of analog voltages on the respective wires of the multi-wire bus according to a respective row of the set of rows of the non-simple orthogonal or unitary matrix.

2. The method of claim 1 , wherein the sequence of binary data bits corresponds to a sequence of vectors of binary data bits, each vector of binary data bits corresponding to a multilevel value.

3. The method of claim 1 , wherein a size of the set of signals is larger than a size of the sequence of binary data bits.

4. The method of claim 1 , wherein the non-simple orthogonal or unitary matrix is a Hadamard matrix.

5. The method of claim 4 , wherein the Hadamard matrix is size 4.

6. The method of claim 4 , wherein the Hadamard matrix is a Sylvester-type Hadamard matrix.

7. The method of claim 1 , wherein each signal is generated as a voltage on the respective wire of the multi-wire bus.

8. The method of claim 1 , wherein each signal is generated as a current on the respective wire of the multi-wire bus.

9. The method of claim 1 , wherein each binary data bit is weighted by a multiplication of the respective row of the set of rows.

10. An apparatus comprising:
an encoder configured to obtain a sequence of binary data bits representing information and to generate a set of signals from the sequence of binary data bits, each signal generated responsive to a weighted summation of the sequence of binary data bits, each binary data bit weighted according to a respective row of a set of rows of a non-simple orthogonal or unitary matrix, the set of rows (i) mutually orthogonal and (ii) the set of rows excludes a row consisting entirely of ones;
a set of signal path drivers configured to transmit the set of signals as a plurality of analog voltages on respective wires of a multi-wire bus; and
a decoder configured to generate a set of outputs representing the information, each output bit of the set of output bits generated in part by forming a respective analog linear combination of the plurality of analog voltages on the respective wires of the multi-wire bus according to a respective row of the set of rows of the non-simple orthogonal or unitary matrix.

11. The apparatus of claim 10 , wherein the sequence of binary data bits corresponds to a sequence of vectors of binary data bits, each vector of binary data bits corresponding to a multilevel value.

12. The apparatus of claim 10 , wherein a size of the set of signals is larger than a size of the sequence of binary data bits.

13. The apparatus of claim 10 , wherein the non-simple orthogonal or unitary matrix is a Hadamard matrix.

14. The apparatus of claim 13 , wherein the Hadamard matrix is size 4.

15. The apparatus of claim 13 , wherein the Hadamard matrix is a Sylvester-type Hadamard matrix.

16. The apparatus of claim 10 , wherein the set of signal path drivers is configured to generate each signal as a voltage on the respective wire of the multi-wire bus.

17. The apparatus of claim 10 , wherein the set of signal path drivers is configured to generate each signal as a current on the respective wire of the multi-wire bus.

18. The apparatus of claim 10 , wherein the encoder is configured to weight each binary data bit by a multiplication of the binary data bit by the respective row of the set of rows.

Assignees

• Ecole Polytechnique Fed Lausanne Epfl

Inventors

• Cronie Harm
• Shokrollahi Amin

Classifications

• H04L25/0272 Primary

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H04L5/0007

  the frequencies being orthogonal, e.g. OFDM(A) or DMT · CPC title

• H04L25/4906

  using binary codes · CPC title

• H04B7/0413 Primary

  MIMO systems · CPC title

• H04B10/54

  Intensity modulation · CPC title