Switching regulator and method of operating the same

US10985654B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10985654-B2
Application numberUS-201916574614-A
CountryUS
Kind codeB2
Filing dateSep 18, 2019
Priority dateMar 11, 2019
Publication dateApr 20, 2021
Grant dateApr 20, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A switching regulator configured to generate a level-controlled output voltage from an input voltage, the switching regulator includes an inductor, an output capacitor configured to generate the level-controlled output voltage based on a current flowing through the inductor, at least two flying capacitors, and a plurality of switches configured to form electrical connections when the switching regulator operates in a first operating mode to, alternately charge each of the at least two flying capacitors using the input voltage, and provide a first boosted voltage to the inductor using a charged flying capacitor among the at least two flying capacitors.

First claim

Opening claim text (preview).

What is claimed is: 1. A switching regulator configured to generate a level-controlled output voltage from an input voltage, the switching regulator comprising: an input node configured to receive the input voltage; an output node configured to output the level-controlled output voltage; an inductor having one end connected to the output node; an output capacitor configured to generate the level-controlled output voltage based on a current flowing through the inductor; a first switch circuit including a plurality of first switches and a first flying capacitor and connected to the input node and the other end of the inductor; a second switch circuit including a plurality of second switches and a second flying capacitor and connected to the input node and the other end of the inductor; and a controller configured to control a switching operation of the first and second switch circuits based on a selected one of a plurality of operation modes, wherein the controller controls the first and second flying capacitors to be synchronously charged in at least one phase or charged in an interleaving manner in a plurality of phases, based on the selected mode and a target level of the level-controlled output voltage. 2. The switching regulator of claim 1 , wherein, when the selected mode is a buck mode, the controller controls the first and second flying capacitors to be synchronously charged and the input voltage to be applied to the other end of the inductor through the first and second switch circuits, in a first phase, and controls the first and second flying capacitors to be synchronously charged, a connection between the first switch circuit and the other end of the inductor to be disconnected, and the other end of the inductor to be grounded through the second switch circuit, in a second phase. 3. The switching regulator of claim 1 , wherein, when the selected mode is a buck-boost mode, the controller controls the input voltage to be boosted through the first and second flying capacitors and applied to the other end of the inductor, in a first phase, controls the first and second flying capacitors to be synchronously charged and the input voltage to be applied to the other end of the inductor through the first and second switch circuits, in a second phase, and controls the first and second flying capacitors to be synchronously charged, a connection between the first switch circuit and the other end of the inductor to be disconnected, and the other end of the inductor to be grounded through the second switch circuit, in a third phase. 4. The switching regulator of claim 1 , wherein, when the selected mode is a boost mode and the target level is less than a reference level, the controller controls the input voltage to be boosted through the first and second flying capacitors and applied to the other end of the inductor, in a first phase, and controls the first and second flying capacitors to be synchronously charged and the input voltage to be applied to the other end of the inductor through the first and second switch circuits, in a second phase. 5. The switching regulator of claim 1 , wherein, when the selected mode is a boost mode, the controller controls the first and second flying capacitors to be synchronously charged when the target level is less than a reference level, and controls the first and second flying capacitors to be charged in an interleaving manner when the target level is greater than or equal to the reference level. 6. The switching regulator of claim 1 , wherein, when the selected mode is a buck mode or a buck-boost mode, the controller controls the first and second flying capacitors to be synchronously charged. 7. The switching regulator of claim 1 , wherein, when the selected mode is a boost mode and the target level is greater than or equal to a reference level, the controller controls the input voltage to be boosted through the first and second flying capacitors and applied to the other end of the inductor, in a first phase, controls the input voltage to be applied to the other end of the inductor through the first switch circuit and controls the second flying capacitor to be charged, in a second phase, controls the first flying capacitor to be charged and the input voltage to be boosted through the second flying capacitor and applied to the other end of the inductor, in a third phase, and controls the first flying capacitor to be charged and the input voltage to be applied to the other end of the inductor through the second switch circuit, in a fourth phase. 8. The switching regulator of claim 7 , wherein the controller controls the first flying capacitor to be floated in the second phase and the second flying capacitor to be floated in the fourth phase. 9. A switching regulator configured to generate a level-controlled output voltage from an input voltage, the switching regulator comprising: an input node configured to receive the input voltage; an output node configured to output the level-controlled output voltage; an inductor having one end connected to the output node; an output capacitor configured to generate the level-controlled output voltage based on a current flowing through the inductor; a first switch circuit including a first connection switch coupled to the input node, a plurality of first switches, and a first flying capacitor and connected to the input node and the other end of the inductor; a second switch circuit including a second connection switch coupled to the input node, a plurality of second switches, and a second flying capacitor and connected to the input node and the other end of the inductor; and a controller configured to control a switching operation of the first and second switch circuits based on a selected one of a plurality of operation modes, wherein the controller controls first and second current paths and third and fourth current paths to be synchronously formed during at least one phase or formed in an interleaving manner during a plurality of phases, in the first and second connection switches, based on the selected mode and a target level of the level-controlled output voltage, wherein the first and second current paths are for respectively charging the first and second flying capacitors with the input voltage and the third and fourth current paths are for applying the input voltage to the other end of the inductor through the first and second switch circuits. 10. The switching regulator of claim 9 , wherein, when the selected mode is a buck mode or a buck-boost mode the controller controls the first and third current paths to be synchronously formed in the first connection switch and controls the second and fourth current paths to be synchronously formed in the second connection switch. 11. The switching regulator of claim 9 , wherein, when the selected mode is a boost mode and the target level is less than a reference level, the controller controls the first and third current paths to be synchronously formed in the first connection switch during a certain phase and controls the second and fourth current paths to be synchronously formed in the second connection switch during the certain phase. 12. The switching regulator of claim 9 , wherein, when the selected mode is a boost mode and the target level is greater than or equal to a reference level, the controller controls the first and third current paths to be formed in an interleaving manner in the first connection switch and controls the second and fourth current paths to be formed in an interleaving manner in the second connection switch. 13. The switching regulator of claim 9 , wherein the controller controls a current less than or equal t

Assignees

Inventors

Classifications

  • H02M3/07Primary

    using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

  • Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck · CPC title

  • H02M3/073Primary

    Charge pumps of the Schenkel-type · CPC title

  • H02M3/1582Primary

    Buck-boost converters (H02M3/1584 takes precedence) · CPC title

  • including plural semiconductor devices as final control devices for a single load · CPC title

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What does patent US10985654B2 cover?
A switching regulator configured to generate a level-controlled output voltage from an input voltage, the switching regulator includes an inductor, an output capacitor configured to generate the level-controlled output voltage based on a current flowing through the inductor, at least two flying capacitors, and a plurality of switches configured to form electrical connections when the switching …
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H02M3/07. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 20 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).